Alternatives and similar repositories for netv2-fpga:

Users that are interested in netv2-fpga are comparing it to the libraries listed below

• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• bunnie / netv2-fpga-basic-overlay
  Vivado design for basic NeTV2 FPGA with chroma-based overlay
  ☆20Updated 8 years ago
• mng2 / AcornCLE215p
  Info and example projects for the SQRL Acorn FPGA board
  ☆10Updated 2 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆36Updated last year
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆29Updated last year
• freecores / mmuart
  Simple RS232 UART
  ☆12Updated 8 years ago
• mithro / displayport-hardware-hacking
  Open Source Hardware Designs for working with DisplayPort and intercepting AUX signals.
  ☆15Updated 5 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 6 years ago
• gatecat / SNES_MiSTer_ulx3s
  SNES for MiSTer
  ☆15Updated 4 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆28Updated 4 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• BLangOS / VexRiscV_with_HW-GDB_Server
  VexRiscV system with GDB-Server in Hardware
  ☆20Updated last year
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• ZipCPU / wbfmtx
  A wishbone controlled FM transmitter hack
  ☆21Updated last year
• jevinskie / litespih4x
  SPI flash MITM and emulation (QSPI is a WIP)
  ☆20Updated 3 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated this week
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆53Updated last year
• jevinskie / liteluna
  LiteX LUNA USB stack integration
  ☆14Updated 2 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆17Updated 10 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated 3 weeks ago
• f32c / tools
  ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)
  ☆22Updated 2 months ago
• stffrdhrn / uart
  Verilog uart receiver and transmitter modules for De0 Nano
  ☆18Updated 10 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• MorgothCreator / VerilogUtilIP
  Here is a bunch of util IPs
  ☆10Updated 6 years ago
• azonenberg / dumptruck
  FPGA based dumper for flashes and more
  ☆12Updated 2 weeks ago
• bunnie / netv2-soc
  NeTV2 SoC based on LiteX
  ☆16Updated 6 years ago
• cyrozap / python-boundary-scan-tools
  Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.
  ☆16Updated 8 years ago
• semify-eda / waveform-generator
  Waveform Generator
  ☆11Updated 2 years ago