A 6800 CPU written in nMigen
☆49Jun 16, 2021Updated 4 years ago
Alternatives and similar repositories for n6800
Users that are interested in n6800 are comparing it to the libraries listed below
Sorting:
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- A tutorial for using nmigen☆313Mar 17, 2021Updated 4 years ago
- I want to learn [n]Migen.☆44Jan 26, 2020Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Oct 31, 2023Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Graded exercises for nMigen (WIP)☆55Dec 25, 2020Updated 5 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆13Jun 14, 2020Updated 5 years ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45May 25, 2025Updated 9 months ago
- A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen☆683Jan 8, 2022Updated 4 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals☆16Jan 11, 2020Updated 6 years ago
- DDR3 controller for nMigen (WIP)☆14Dec 25, 2023Updated 2 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 4 years ago
- Low-cost ECP5 FPGA development board☆80Sep 1, 2020Updated 5 years ago
- Board and connector definition files for nMigen☆30Sep 22, 2020Updated 5 years ago
- ice40 USB Analyzer☆57Aug 8, 2020Updated 5 years ago
- All Digital Radio Platform written in nmigen targeting FPGAs (for now)☆81Jun 1, 2021Updated 4 years ago
- SWD Programmer for PSoc4 based devices☆32Aug 30, 2015Updated 10 years ago
- RCA COSMAC CDP1802 functional equivalent CPU core in VHDL☆27Jan 7, 2018Updated 8 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- A low-cost remote vital signs monitor for home patients☆12Feb 19, 2026Updated 2 weeks ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Jan 22, 2026Updated last month
- Simple but Small Frame Grabber☆38Nov 22, 2021Updated 4 years ago
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆259Aug 21, 2023Updated 2 years ago
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 4 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆63Nov 5, 2021Updated 4 years ago
- Resource-efficient 16-bit CPU architecture for FPGA control plane☆96Feb 20, 2025Updated last year
- Example litex Risc-V SOC and some example code projects in multiple languages.☆71May 11, 2023Updated 2 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- IPDBG☆13Aug 22, 2025Updated 6 months ago
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- A-Frame multi-user Croquet component☆12Aug 23, 2024Updated last year
- ☆17Nov 25, 2017Updated 8 years ago
- DA14580/murata module PCBs☆10Jul 30, 2017Updated 8 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Sep 2, 2023Updated 2 years ago
- ice40 UltraPlus demos☆23Oct 12, 2020Updated 5 years ago