Implementation of a fully-functional digital signal oscilloscope written in Verilog HDL. Tested on a DE-1 SoC 5CSEMA5F31C6 FPGA board. Uses a VGA monitor for displaying.
☆24Aug 25, 2023Updated 2 years ago
Alternatives and similar repositories for Digital-Signal-Oscilloscope
Users that are interested in Digital-Signal-Oscilloscope are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design, Documentation, Schematic, Board, Code files for the FPGA Oscilloscope project using an Altera Cyclone III FPGA.☆123Jul 5, 2014Updated 11 years ago
- LiteX based FPGA gateware for Thunderscope.☆30Mar 23, 2026Updated 3 weeks ago
- MS-DOS 2.0 restoration project☆10Apr 5, 2024Updated 2 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- Trajectory Estimation with IMU and GPS Data (Sensor Data Fusion)☆11Mar 23, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Gerber file for an arduino based transistor curve tracer☆13May 23, 2022Updated 3 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- ☆11Dec 10, 2025Updated 4 months ago
- ☆13Nov 14, 2022Updated 3 years ago
- Pong game on an FPGA in Verilog.☆58Feb 8, 2012Updated 14 years ago
- 浙大校徽全集，复制图片链接，方便在md中使用☆37Nov 17, 2024Updated last year
- Misc iCE40 specific cores☆14Feb 13, 2023Updated 3 years ago
- SwapForth J1a processor for Icestudio☆12Aug 28, 2020Updated 5 years ago
- Develop and run MATLAB from nvim☆22Apr 1, 2026Updated 2 weeks ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A basic desktop analog computer☆20Mar 2, 2022Updated 4 years ago
- Hardware Implementation of low-bit rate Codec, Codec2 in Verilog RTL on Cyclone IV FPGA.☆15Mar 29, 2020Updated 6 years ago
- A newbie-friendly, temporary solution that encourages all contributions for long-term and stable use for MT7902 driver on Linux☆14Aug 6, 2024Updated last year
- MicroPython on FPGA☆13Jul 11, 2016Updated 9 years ago
- ☆16Aug 9, 2023Updated 2 years ago
- ☆15Apr 19, 2017Updated 9 years ago
- Let's write an OS which can run on ARM in Rust from scratch! (🚧WIP)☆17Mar 13, 2022Updated 4 years ago
- 基于小脚丫FPGA的电子琴，模拟钢琴音色，支持127个音符演奏，可通过转化MIDI文件实现自动播放☆15Aug 22, 2022Updated 3 years ago
- ☆14Dec 18, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Project 2.2 Frequency counter☆12May 30, 2025Updated 10 months ago
- A collection of gmid scripts and Data to plot various parameters needed for gm/id based design methodology using open source tools and Go…☆15Nov 4, 2025Updated 5 months ago
- Modification of grbl that computes motor steps based on a SCARA coordinate system. Grbl is open source, embedded, high performance g-code…☆20Mar 28, 2021Updated 5 years ago
- A fast C++ Madelbrot renderer using AVX2 extensions☆13Oct 7, 2022Updated 3 years ago
- an object oriented event loop for linux☆29Aug 18, 2011Updated 14 years ago
- OV7670 camera, ST7735 screen and others on ice40 ultraplus fpga (breakout board)☆16Jun 14, 2020Updated 5 years ago
- An AXI DDR3 SDRAM controller for FPGA☆46Dec 30, 2023Updated 2 years ago
- This repo presents Markus' ComponentTester firmware (https://github.com/Mikrocontroller-net/transistortester/tree/master/Software/Markus …☆51Updated this week
- ☆18Dec 28, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- OK:iCE40Pro, based on iCE40up5k FPGA Core, is an Open Source Educational FPGA GamePad Console.☆15May 6, 2023Updated 2 years ago
- Faust major mode for editing faust code (.dsp files)☆16Oct 4, 2020Updated 5 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- A design for TinyTapeout☆19Sep 23, 2022Updated 3 years ago
- An LLVM pass to prove that an II works for the given loop for Vitis HLS☆11Aug 22, 2021Updated 4 years ago
- network packets capture in C language based on libpcap☆14Sep 23, 2022Updated 3 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 6 months ago