Basic Simulink Blocks for modeling CDRs and PLLs
☆15Apr 25, 2020Updated 5 years ago
Alternatives and similar repositories for Wireline-Simulink
Users that are interested in Wireline-Simulink are comparing it to the libraries listed below
Sorting:
- ☆11Apr 25, 2020Updated 5 years ago
- Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation☆14Apr 25, 2020Updated 5 years ago
- ☆16Feb 5, 2026Updated 3 weeks ago
- An EDA tool for automatic device sizing using Gm/Id method.☆14Jan 10, 2026Updated last month
- All Digital Phase-Locked Loop (ADPLL)☆27Jan 16, 2024Updated 2 years ago
- ☆24Jul 2, 2024Updated last year
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 2 years ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆71Apr 9, 2018Updated 7 years ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 3 years ago
- Лабораторные работы по ЦОС (python)☆10Apr 28, 2025Updated 10 months ago
- GPTIPS2F: Symbolic Regression toolbox for MATLAB evolved☆11Jun 10, 2022Updated 3 years ago
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 11 years ago
- Port of the LLVM compiler infrastructure to the time-predictable processor Patmos☆15Apr 2, 2025Updated 11 months ago
- Advanced Integrated Circuits 2025☆13Nov 1, 2025Updated 4 months ago
- sample VCD files☆43Feb 13, 2026Updated 2 weeks ago
- A tool for modeling FSMs by VHDL or Verilog☆11Updated this week
- ☆11Sep 26, 2023Updated 2 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- My personal Electronics projects versioning repo.☆13Dec 9, 2013Updated 12 years ago
- A mini development environment for developing and troubleshooting the Cypress PSoC Digital Filter Block☆11Mar 23, 2020Updated 5 years ago
- 用AI从0开始制作“研究生模拟器”小游戏☆42Jan 20, 2026Updated last month
- Notes on Diffy Qs, a textbook for differential equations☆10Jun 8, 2023Updated 2 years ago
- Ten Thousand Failures Blog☆12Jul 22, 2014Updated 11 years ago
- An interactive GUI to draw numbers and recognize them using a CNN written with Keras and trained with MNIST☆10Dec 26, 2017Updated 8 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- All Digital Phase-Locked Loop☆12May 22, 2023Updated 2 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- SSLsplit for OpenWRT. Makefile + Sources☆12May 6, 2020Updated 5 years ago
- Simple IIO FM Radio receive example☆16Feb 23, 2026Updated last week
- Software-Hardware Implementation of IEEE 802.11a Wifi Standard☆14Apr 17, 2023Updated 2 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- SystemVerilog Example Files☆11Jan 15, 2013Updated 13 years ago
- Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignore…☆10Jan 27, 2026Updated last month
- A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the fr…☆12Jul 3, 2025Updated 8 months ago
- Yet another implementation of TI C6x DSP simulator☆12Jan 16, 2014Updated 12 years ago
- PlutoSDR GNURadio WFM stereo demodulation, and using PlutoSDR as standalone radio with customised Firmware☆13Feb 18, 2021Updated 5 years ago
- Vector Fitting☆15Apr 7, 2022Updated 3 years ago
- ☆14Jul 12, 2013Updated 12 years ago
- Example of a full DC synthesis script for a simple design☆13Feb 25, 2019Updated 7 years ago