Alternatives and similar repositories for Wireline-Simulink

Users that are interested in Wireline-Simulink are comparing it to the libraries listed below

• rggen / rggen-sample-testbench
  ☆14Updated 3 weeks ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 4 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• mbits-mirafra / i3c_avip
  Verification IP project for I3C protocol
  ☆19Updated 6 months ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆18Updated 2 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆20Updated last week
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 3 months ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 7 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• rggen / rggen-systemverilog
  SystemVerilog RTL and UVM RAL model generators for RgGen
  ☆14Updated 3 weeks ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 11 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆27Updated 3 weeks ago
• sjaeckel / axi-bfm
  git clone of http://code.google.com/p/axi-bfm/
  ☆17Updated 12 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated 9 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆61Updated 3 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆24Updated 5 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆32Updated 4 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆35Updated 8 months ago
• liuguangxi / gng
  Gaussian noise generator Verilog IP core
  ☆31Updated 2 years ago