π» Simple Undertale-like game on Basys3 FPGA written in Verilog
β16Jul 3, 2020Updated 6 years ago
Alternatives and similar repositories for Undertale-Verilog
Users that are interested in Undertale-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- βHardware Synthesis Laboratory Using Verilogβ41May 10, 2020Updated 6 years ago
- This is part of EC383 - Mini Project in VLSI Design.β10May 8, 2022Updated 4 years ago
- All switching software as well as control software for a physically and emulated capable network coding switch. FPGA Acceleration added .β¦β10Nov 19, 2019Updated 6 years ago
- Speed up development of AF_XDP-based Network Functionsβ14Jul 16, 2023Updated 3 years ago
- β11Mar 30, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer β’ AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An FPGA-CPU co-design framework for accelerating software NFs (Network Functions) with Intel DPDKβ13May 27, 2020Updated 6 years ago
- A very minimal game with a player, enemies, and a goal (that's it!)β21Sep 20, 2019Updated 7 years ago
- Image Stiching for Panoramic Imagesβ10May 15, 2013Updated 13 years ago
- Live Chat Controller application is desktop application for get live chat to control your pcβ17May 12, 2021Updated 5 years ago
- A MIPS32 System-on-Chip for the DE0-Nano FPGAβ12Sep 1, 2014Updated 12 years ago
- β21Nov 13, 2018Updated 7 years ago
- β17Jun 25, 2026Updated 4 months ago
- Simple table tennis game implemented in Verilog for the DE0-Nanoβ14Sep 27, 2019Updated 7 years ago
- Machine Vision for NVIDIA Jetson. GPU accelerated video capture and neural networks for real-time object detection.β11Nov 12, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- API server for converts hwp files - thanks to hwplib & hwpxlibβ13Jun 9, 2023Updated 3 years ago
- Study Buddy Promptβ15Jul 31, 2025Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction setβ16Jan 14, 2021Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-maβ¦β15Dec 23, 2022Updated 3 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) β¦β12Sep 18, 2025Updated last year
- 10 Gigabit Ethernet MAC Core UVM Verificationβ19Oct 5, 2023Updated 3 years ago
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for β¦β17Oct 24, 2017Updated 9 years ago
- NLP @chula 2021β63May 1, 2021Updated 5 years ago
- β14Aug 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Course material for Purdue ECE57000 Artificial Intelligenceβ16Nov 8, 2018Updated 7 years ago
- The course contest involves a multi-player capture-the-flag variant of Pacman, where agents control both Pacman and ghosts in coordinatedβ¦β12Jan 24, 2021Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.β23Oct 24, 2023Updated 3 years ago
- Python script to download Instagram livestreams.β14Sep 4, 2026Updated 2 months ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Botβ¦β17Aug 21, 2018Updated 8 years ago
- Slides of Dr Sparsh Mittal on "Computer Architecture for AI" (aka Hardware Architecture for Deep Learning) Courseβ19Apr 20, 2026Updated 6 months ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effβ¦β17Aug 26, 2021Updated 5 years ago
- Integration of two camera π· modules to Basys 3 FPGAβ48Feb 8, 2023Updated 3 years ago
- Morpheus: Domain Specific Run Time Optimization for Software Data Planes -- Presented at ASPLOS22β36Apr 11, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean β’ AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Synchronous FIFOs designed in Verilog/System Verilog.β26Dec 21, 2025Updated 10 months ago
- System for detecting vein patterns.β22Apr 5, 2020Updated 6 years ago
- An inhouse RISC-V 32-bits CPUβ22Updated this week
- β29Mar 13, 2022Updated 4 years ago
- A complete UVM TB for verification of single port 64KB RAMβ18Apr 16, 2021Updated 5 years ago
- β38Oct 12, 2026Updated 3 weeks ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Playerβ28Sep 2, 2019Updated 7 years ago