Alternatives and similar repositories for Undertale-Verilog

Users that are interested in Undertale-Verilog are comparing it to the libraries listed below

• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆153Updated 6 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆138Updated 5 years ago
• yang-le / riscv_cpu
  a simple riscv cpu
  ☆22Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆315Updated 7 years ago
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆16Updated last year
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆137Updated 5 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆55Updated last year
• Test134n / 32-Verilog-Mini-Projects
  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …
  ☆20Updated 3 months ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆230Updated 8 years ago
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆217Updated 5 months ago
• maze1377 / pipeline-mips-verilog
  A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
  ☆53Updated 9 months ago
• vipinkmenon / neuralNetwork
  ☆291Updated last year
• FPGADude / Digital-Design
  Verilog HDL files
  ☆157Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆75Updated 6 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆207Updated 6 years ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆161Updated 4 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆365Updated 2 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆112Updated 4 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆168Updated last year
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆160Updated last year
• TheLeopardsH / RISC-V-5-stage-pipelined-in-verilog
  RISC-V-5 stage pipelined in verilog
  ☆10Updated 5 years ago
• neelkshah / MIPS-Processor
  5-stage pipelined 32-bit MIPS microprocessor in Verilog
  ☆135Updated 5 years ago
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆17Updated last year
• pendkeomkar / SPI
  Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…
  ☆19Updated 7 years ago
• ShichenQiao / ECE554_SP23_FPGA_Handwriting_Recognition
  Senior Design Project at UW-Madison ECE
  ☆16Updated 2 years ago
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆58Updated 2 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆67Updated 3 years ago
• qninth / awesome-digital-ic
  A collection of great digital IC project/tutorial/website etc..
  ☆128Updated 3 years ago
• govardhnn / RISC_V_Single_Cycle_Processor
  My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition …
  ☆30Updated 2 years ago
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago