π» Simple Undertale-like game on Basys3 FPGA written in Verilog
β16Jul 3, 2020Updated 6 years ago
Alternatives and similar repositories for Undertale-Verilog
Users that are interested in Undertale-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- βHardware Synthesis Laboratory Using Verilogβ40May 10, 2020Updated 6 years ago
- RISC-V kernel step-by-step implmenetationβ12Nov 12, 2019Updated 6 years ago
- All switching software as well as control software for a physically and emulated capable network coding switch. FPGA Acceleration added .β¦β10Nov 19, 2019Updated 6 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/β14Dec 4, 2018Updated 7 years ago
- An FPGA-CPU co-design framework for accelerating software NFs (Network Functions) with Intel DPDKβ13May 27, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer β’ AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction setβ15Jan 14, 2021Updated 5 years ago
- A very minimal game with a player, enemies, and a goal (that's it!)β20Sep 20, 2019Updated 6 years ago
- β11Mar 30, 2022Updated 4 years ago
- Live Chat Controller application is desktop application for get live chat to control your pcβ17May 12, 2021Updated 5 years ago
- Building a Computer From Scratch with verilogβ11Feb 6, 2026Updated 5 months ago
- β21Nov 13, 2018Updated 7 years ago
- π§ Real-time data streaming from NeuroSky MindWave Mobile Headsetβ10Jul 17, 2020Updated 5 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) β¦β12Sep 18, 2025Updated 9 months ago
- β16Mar 27, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean β’ AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.β29Sep 4, 2025Updated 10 months ago
- Cycle accurate FPGA implementation of various 6502 CPU variantsβ28May 7, 2022Updated 4 years ago
- An inhouse RISC-V 32-bits CPUβ20Feb 12, 2026Updated 4 months ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effβ¦β16Aug 26, 2021Updated 4 years ago
- The course contest involves a multi-player capture-the-flag variant of Pacman, where agents control both Pacman and ghosts in coordinatedβ¦β12Jan 24, 2021Updated 5 years ago
- Simple Tensorflow implementation of "MirrorGAN: Learning Text-to-image Generation by Redescription" (CVPR 2019)β15Mar 23, 2020Updated 6 years ago
- NLP @chula 2021β63May 1, 2021Updated 5 years ago
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for β¦β17Oct 24, 2017Updated 8 years ago
- 10 Gigabit Ethernet MAC Core UVM Verificationβ19Oct 5, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient β’ AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Synchronous FIFOs designed in Verilog/System Verilog.β25Dec 21, 2025Updated 6 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.β23Oct 24, 2023Updated 2 years ago
- Practices related to the fundamental level of the programming language Verilog.β13Jan 16, 2023Updated 3 years ago
- Networking Template Library for Vivado HLSβ29Jul 12, 2020Updated 5 years ago
- [NeurIPS'24] "NeuralFuse: Learning to Recover the Accuracy of Access-Limited Neural Network Inference in Low-Voltage Regimes" by Hao-Lun β¦β10Sep 18, 2025Updated 9 months ago
- Morpheus: Domain Specific Run Time Optimization for Software Data Planes -- Presented at ASPLOS22β36Apr 11, 2024Updated 2 years ago
- π¬ A collection for those AI (RL / DL / SL / Evoluation / Genetic Algorithm) used in financial market. otherwise, we add Technology Analyβ¦β13Mar 17, 2024Updated 2 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Botβ¦β17Aug 21, 2018Updated 7 years ago
- System for detecting vein patterns.β21Apr 5, 2020Updated 6 years ago
- Virtual machines for every use case on DigitalOcean β’ AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-Vβ¦β29Aug 28, 2024Updated last year
- miniSpartan6+ (Spartan6) FPGA based MP3 Playerβ27Sep 2, 2019Updated 6 years ago
- Domain Adaptation of Thai Word Segmentation Models using Stacked Ensemble (EMNLP2020)β19Feb 2, 2024Updated 2 years ago
- Tutorial for BeeInvaders game on the Basys3 FPGA boardβ12Jul 17, 2023Updated 2 years ago
- β37Apr 10, 2026Updated 2 months ago
- A Project of a Reinforcement Learning course. Simulated competing investment strategies through continuous refinement in a virtual stock β¦β15Aug 26, 2019Updated 6 years ago
- This repository contains code for paper VICTR: Visual Information Captured Text Representation for Text-to-Image Multimodal Tasksβ14Nov 20, 2021Updated 4 years ago