An inhouse RISC-V 32-bits CPU
☆18Feb 12, 2026Updated last month
Alternatives and similar repositories for synapse32
Users that are interested in synapse32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆10Sep 19, 2025Updated 6 months ago
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆23Sep 4, 2025Updated 6 months ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- ☆14May 24, 2025Updated 10 months ago
- ☆11May 8, 2022Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Tutorial on how to boot Zephyr on the Avnet/Digilent Zedboard, includes building a FPGA bitstream and the First Stage Boot Loader (FSBL)☆19Sep 21, 2024Updated last year
- "The measure of greatness in a scientific idea is the extent to which it stimulates thought and opens up new lines of research."― Paul Di…☆17Feb 27, 2021Updated 5 years ago
- TinyQV - Crowdsourced Risc-V SoC☆36Oct 20, 2025Updated 5 months ago
- 同济大学计算机组成原理课程设计,包括31条单周期cpu和54条多周期cpu☆20Jul 5, 2023Updated 2 years ago
- Slash Sim is a simple C based RV32 Instruction set simulator. This can be used to simulate any binary file that is compiled using RISCV t…☆21Jan 14, 2025Updated last year
- Labs for the Ibex Demo System☆17Nov 18, 2023Updated 2 years ago
- Built a test environment using UVM Methodology to verify APB Protocol.☆15Feb 6, 2019Updated 7 years ago
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- ☆11Nov 17, 2025Updated 4 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆18Jan 12, 2023Updated 3 years ago
- This is our Compiler Design project for 6th semester.☆12May 15, 2022Updated 3 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆17Sep 10, 2025Updated 6 months ago
- ☆25Apr 13, 2025Updated 11 months ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆52Mar 5, 2026Updated 3 weeks ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- Codify on iPad utilizing Wasix and CoreML☆46Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated last month
- Github Pages template for academic portfolio websites☆16Oct 22, 2024Updated last year
- ☆21Jul 28, 2016Updated 9 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 6 months ago
- ☆12Jul 2, 2024Updated last year
- ☆16Mar 27, 2024Updated last year
- hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel☆16Nov 15, 2024Updated last year
- ☆15Apr 18, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- The starting place for all example code to get up and running using a Bracket Bot.☆54Jun 16, 2025Updated 9 months ago
- kamera is a simulation toolkit for observing, analyzing, and verifying the behavior of Kubernetes control planes.☆65Mar 13, 2026Updated last week
- A minimal BASIC interpreter for Arduino UNO (ATmega328P).☆37Jan 18, 2026Updated 2 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆72Feb 12, 2026Updated last month
- Arduino Library for the AFE4490 SPO2 shield and breakout boards from Protocentral☆10Oct 31, 2025Updated 4 months ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year