SRA-VJTI / synapse32Links
An inhouse RISC-V 32-bits CPU
☆18Updated 5 months ago
Alternatives and similar repositories for synapse32
Users that are interested in synapse32 are comparing it to the libraries listed below
Sorting:
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆129Updated 2 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- SystemVerilog Tutorial☆185Updated 2 weeks ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Design Verification Engineer interview preparation guide.☆41Updated 5 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆125Updated 2 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆31Updated last year
- ☆45Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆175Updated this week
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆81Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- ☆17Updated 2 years ago
- ☆17Updated 6 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- Complete tutorial code.☆22Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- A reference book on System-on-Chip Design☆37Updated 6 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆38Updated 3 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Verilog/SystemVerilog Guide☆75Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- Open source ISS and logic RISC-V 32 bit project☆61Updated last week
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago