SRA-VJTI / synapse32View external linksLinks
An inhouse RISC-V 32-bits CPU
☆18Jun 21, 2025Updated 7 months ago
Alternatives and similar repositories for synapse32
Users that are interested in synapse32 are comparing it to the libraries listed below
Sorting:
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆10Sep 19, 2025Updated 4 months ago
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆22Sep 4, 2025Updated 5 months ago
- Slash Sim is a simple C based RV32 Instruction set simulator. This can be used to simulate any binary file that is compiled using RISCV t…☆20Jan 14, 2025Updated last year
- This is our Compiler Design project for 6th semester.☆12May 15, 2022Updated 3 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 2 years ago
- 5 stage pipeline implementation of RISC-V 32I Processor.☆10Nov 27, 2024Updated last year
- ☆14May 24, 2025Updated 8 months ago
- This is a repository about how you can Controll KK 2.1.5 flght Controller by using the Rapsberry pi 3.☆12Sep 19, 2019Updated 6 years ago
- Simple Python script to download the entirety of Wikipedia on a weekly basis.☆13May 2, 2025Updated 9 months ago
- Arduino Library for the AFE4490 SPO2 shield and breakout boards from Protocentral☆10Oct 31, 2025Updated 3 months ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- DMA Project using Verilog HDL☆13Dec 26, 2019Updated 6 years ago
- ☆11May 8, 2022Updated 3 years ago
- ☆11Nov 17, 2025Updated 2 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- ☆16Mar 27, 2024Updated last year
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆13Sep 18, 2025Updated 4 months ago
- Building a Computer From Scratch with verilog☆10Feb 6, 2026Updated last week
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆15Sep 10, 2025Updated 5 months ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 6 months ago
- Built a test environment using UVM Methodology to verify APB Protocol.☆15Feb 6, 2019Updated 7 years ago
- Automatically take screenshots of comments!☆10Jan 30, 2022Updated 4 years ago
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- ☆16May 10, 2019Updated 6 years ago
- ☆13Feb 1, 2025Updated last year
- ☆11Jul 2, 2024Updated last year
- Deep learning tutorials☆18Jan 31, 2026Updated 2 weeks ago
- C Library for ST7789 1.69 TFT LCD display☆12Jun 3, 2024Updated last year
- ☆14Jul 23, 2020Updated 5 years ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- Tutorial on how to boot Zephyr on the Avnet/Digilent Zedboard, includes building a FPGA bitstream and the First Stage Boot Loader (FSBL)☆19Sep 21, 2024Updated last year
- imported from https://dangerous-prototypes-open-hardware.googlecode.com/svn/branches/pyBusPirate☆15Jul 24, 2020Updated 5 years ago
- Opensource HAL API Library for AVR Microcontrollers.☆12Oct 22, 2020Updated 5 years ago
- Web application to record speech for an open data set☆13Apr 6, 2021Updated 4 years ago
- ☆13Apr 24, 2022Updated 3 years ago
- Bus Pirate 5 Hardware Documentation☆13May 28, 2025Updated 8 months ago
- ☆17Oct 28, 2024Updated last year