verilog-meetup / systemverilog-microarchitecture-challenge-for-ai-2Links
SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.
☆19Updated 3 weeks ago
Alternatives and similar repositories for systemverilog-microarchitecture-challenge-for-ai-2
Users that are interested in systemverilog-microarchitecture-challenge-for-ai-2 are comparing it to the libraries listed below
Sorting:
- An inhouse RISC-V 32-bits CPU☆17Updated 3 months ago
- ☆16Updated 3 months ago
- ☆36Updated 3 months ago
- ☆14Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 9 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- A demo system for Ibex including debug support and some peripherals☆76Updated 3 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆65Updated last week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆115Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆139Updated last month
- Open source ISS and logic RISC-V 32 bit project☆58Updated 3 months ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆59Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆109Updated last year
- Control and status register code generator toolchain☆145Updated this week
- A simple DDR3 memory controller☆59Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 8 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated this week
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆63Updated 10 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆110Updated last year
- Making cocotb testbenches that bit easier☆36Updated 2 months ago
- Verilog digital signal processing components☆156Updated 2 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 3 months ago
- SystemVerilog Tutorial☆172Updated 4 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆63Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆79Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago