SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.
☆23Sep 4, 2025Updated 6 months ago
Alternatives and similar repositories for systemverilog-microarchitecture-challenge-for-ai-2
Users that are interested in systemverilog-microarchitecture-challenge-for-ai-2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Mar 12, 2021Updated 5 years ago
- An inhouse RISC-V 32-bits CPU☆18Feb 12, 2026Updated last month
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- ☆25Sep 17, 2025Updated 6 months ago
- Драйвер OLED дисплеев на чипах SSD1306 или SH1106 для STM32 на HAL с русскими и английскими шрифтами☆12May 18, 2019Updated 6 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- GitHub Repository for the HW CWE SIG☆17Updated this week
- This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains ever…☆36Jul 29, 2024Updated last year
- BluePill+ GD32 Series, GD32F103CBT6☆11Jun 19, 2022Updated 3 years ago
- RTL Design and Verification☆18Jan 4, 2021Updated 5 years ago
- Official Website of Tesla NIT, Patna☆19Aug 31, 2025Updated 6 months ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆15Mar 8, 2026Updated 3 weeks ago
- This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options☆13Jan 28, 2024Updated 2 years ago
- （Not actively updating）Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆20Dec 29, 2024Updated last year
- 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus☆11Jan 5, 2018Updated 8 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- ☆22Jul 16, 2020Updated 5 years ago
- Image Stiching for Panoramic Images☆10May 15, 2013Updated 12 years ago
- TUM EI Master Course "SmartCard Lab" at https://www.master.ei.tum.de/?id=125☆12Aug 13, 2015Updated 10 years ago
- This is a passion project where I aim to explore the RTL design topics of my interest.☆13May 23, 2025Updated 10 months ago
- ☆21Apr 8, 2025Updated 11 months ago
- Building a Computer From Scratch with verilog☆11Feb 6, 2026Updated last month
- Find best material to prepare for Gate Electronics and Communication Engineering.☆36Feb 20, 2024Updated 2 years ago
- A curated list of awesome interactive web experiences☆13Jan 12, 2017Updated 9 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A tool for quick analysis of data from a serial device.☆15Nov 25, 2024Updated last year
- Learning Path: RISC-V & Advanced Edge AI on SiFive FE310-G002 SoC | 32-bit RISC-V | 320 MHz | 16KB L1 Instruction Cache | 128Mbit (16MB) …☆12Sep 18, 2025Updated 6 months ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆33Jan 18, 2025Updated last year
- ☆16Mar 27, 2024Updated 2 years ago
- ☆21Oct 23, 2020Updated 5 years ago
- microKanren sagittarius/larceny☆11Jun 13, 2015Updated 10 years ago
- Provide user-defined initialization semantics for arithmetic types.☆12Aug 26, 2018Updated 7 years ago
- ☆12Sep 27, 2022Updated 3 years ago
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆34Aug 4, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Codebase to simulate production code with NS3 using Docker Containers☆10Oct 10, 2019Updated 6 years ago
- ☆52Aug 7, 2025Updated 7 months ago
- GNU Guix zephyrRTOS integration☆16Sep 25, 2025Updated 6 months ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- ☆10Nov 23, 2015Updated 10 years ago
- STM32H7B0VBT6 Core Board 280Mhz,128KB ROM,1.4M SRAM☆17Nov 20, 2022Updated 3 years ago
- This repository includes codes created for a graduate level Perception course at the University of Maryland. The repo includes codes for …☆17Oct 24, 2017Updated 8 years ago