mmxsrup / axi4-interface
AXI4 and AXI4-Lite interface definitions
☆94Updated 4 years ago
Alternatives and similar repositories for axi4-interface:
Users that are interested in axi4-interface are comparing it to the libraries listed below
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- An AXI4 crossbar implementation in SystemVerilog☆142Updated this week
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 11 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆59Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆165Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆171Updated 2 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- DDR2 memory controller written in Verilog☆76Updated 13 years ago
- AXI Interconnect☆47Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- AHB3-Lite Interconnect☆88Updated 11 months ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆67Updated last year
- round robin arbiter☆72Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆95Updated last year
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- ☆36Updated 9 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆139Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- ☆48Updated 2 years ago