Alternatives and similar repositories for axi4-interface:

Users that are interested in axi4-interface are comparing it to the libraries listed below

• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 6 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆95Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆106Updated 10 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆31Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆131Updated 2 months ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆86Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆31Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆55Updated 4 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆159Updated 2 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆60Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆83Updated 9 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆165Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆59Updated last year
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆137Updated 6 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• ForrestBlue / cortexm0ds
  ☆57Updated 9 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆61Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆109Updated 7 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆96Updated last month
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆32Updated 7 years ago