Alternatives and similar repositories for easyUVM:

Users that are interested in easyUVM are comparing it to the libraries listed below

• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• hjking / uvm_gen
  UVM Generator
  ☆44Updated 10 months ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆42Updated 5 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆54Updated 6 months ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆36Updated last year
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆43Updated 3 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆47Updated 10 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• Juniper / simple_reg_model
  System verilog register model for uvm testbenches.
  ☆19Updated 6 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆68Updated 5 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆31Updated 7 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆60Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 4 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 3 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆31Updated 4 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆38Updated 4 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆37Updated 5 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆58Updated 4 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆78Updated 7 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆32Updated 7 years ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆45Updated 9 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆19Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆42Updated 10 months ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆52Updated last year
• Lampro-Mellon / apb-uart-uvm-env
  ☆38Updated last year
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆81Updated 4 months ago
• JoseIuri / Simple_UVM
  Implements a simple UVM based testbench for a simple memory DUT.
  ☆12Updated 5 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆41Updated 3 years ago