Alternatives and similar repositories for PIMeval-PIMbench

Users that are interested in PIMeval-PIMbench are comparing it to the libraries listed below

• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 4 years ago
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆46Updated 4 months ago
• hplp / PiMulator
  Processing in Memory Emulation
  ☆22Updated 2 years ago
• scale-snu / attacc_simulator
  ☆112Updated last year
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆44Updated 2 years ago
• Aayush-Ankit / puma-simulator
  [ASPLOS 2019] PUMA-simulator provides a detailed simulation model of a dataflow architecture built with NVM (non-volatile memory), and ru…
  ☆68Updated 2 years ago
• VIA-Research / uPIMulator
  ☆155Updated 10 months ago
• UniNDP-hpca25-ae / UniNDP
  Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"
  ☆48Updated 3 months ago
• 7bvcxz / PIMsim
  ☆18Updated 2 years ago
• CMU-SAFARI / MIMDRAM
  Source code for the architectural simulator used for modeling the PUD system proposed in our HPCA 2024 paper `MIMDRAM: An End-to-End Proc…
  ☆28Updated 2 months ago
• illinois-impact / puma-compiler
  PUMA Compiler
  ☆30Updated last month
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆22Updated last year
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆66Updated last month
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆73Updated 2 years ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆96Updated last year
• CMU-SAFARI / Sectored-DRAM
  A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…
  ☆12Updated last year
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 8 months ago
• topanitanw / Cacti-7.0
  ☆19Updated 7 months ago
• casys-kaist / NeuPIMs
  NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing
  ☆102Updated last year
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated 2 years ago
• Xtra-Computing / ReGraph
  Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines
  ☆22Updated 3 years ago
• UCLA-VAST / Serpens
  Serpens is an HBM FPGA accelerator for SpMV
  ☆22Updated last year
• PSAL-POSTECH / M2NDP-public
  A Cycle-level simulator for M2NDP
  ☆32Updated 3 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆49Updated 6 months ago
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆208Updated 11 months ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆84Updated 6 years ago
• Zhaoshixin-sky / CIM-MLC
  [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
  ☆45Updated last year
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆147Updated 5 months ago