This simulator models multi core systems with primary focus on the memory hierarchy. It models a trace-based out-of-order core frontend and memory scheduling policies like FRFCFS, ATLAS, TCM and slowdown estimation models, ASM and MISE. Based on the MICRO 2015 paper at https://users.ece.cmu.edu/~omutlu/pub/application-slowdown-model_micro15.pdf
☆12Feb 12, 2016Updated 10 years ago
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