coltonshane / WAVE-VivadoLinks
HDL and C source for WAVE Zynq Ultrascale+ SoC
☆18Updated 3 years ago
Alternatives and similar repositories for WAVE-Vivado
Users that are interested in WAVE-Vivado are comparing it to the libraries listed below
Sorting:
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 7 years ago
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- ☆30Updated 8 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- LMAC Core1 - Ethernet 1G/100M/10M☆17Updated 2 years ago
- Open FPGA Modules☆24Updated 9 months ago
- PNG encoder, implemented in VHDL☆23Updated last year
- VHDL PCIe Transceiver☆28Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 4 months ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆62Updated last week
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- Open source FPGA-based NIC and platform for in-network compute☆66Updated 8 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆65Updated last week
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆94Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆39Updated 3 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 6 years ago
- ☆18Updated 4 years ago
- ☆69Updated 3 years ago
- UART models for cocotb☆29Updated 2 years ago
- ☆18Updated 3 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆16Updated 6 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year