ucb-ee290c / sp21-aes-rocc-accelView external linksLinks
AES RoCC Accelerator
☆10May 20, 2021Updated 4 years ago
Alternatives and similar repositories for sp21-aes-rocc-accel
Users that are interested in sp21-aes-rocc-accel are comparing it to the libraries listed below
Sorting:
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- Original test vector of RISC-V Vector Extension☆14Mar 23, 2021Updated 4 years ago
- RISC-V IOMMU Demo (Linux & Bao)☆24Dec 5, 2023Updated 2 years ago
- TEE hardware - based on the chipyard repository - hardware to accelerate TEE☆24Dec 16, 2022Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆13Mar 26, 2024Updated last year
- ☆38Dec 8, 2024Updated last year
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆40Jan 2, 2026Updated last month
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 4 months ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Linux integrity monitoring for CentOS/RHEL☆10May 13, 2020Updated 5 years ago
- VMSDK implements the Evidence API☆11Nov 25, 2024Updated last year
- A simple 8086-CPU simulator using Verilog and Quartus II☆10Jul 9, 2018Updated 7 years ago
- ☆11May 8, 2022Updated 3 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Code repository for experiments in SpecROP paper☆13Sep 3, 2021Updated 4 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- Public repository of the UCSC CMPE220 class project☆10Oct 8, 2017Updated 8 years ago
- A memory allocator that aims to eliminate dangling pointer vulnerabilities at a low overhead, using virtualisation via Dune. My Computer …☆10Nov 27, 2019Updated 6 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- OPAE porting to Xilinx FPGA devices.☆39Aug 5, 2020Updated 5 years ago
- ☆11Mar 10, 2023Updated 2 years ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Updated this week
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆11Apr 21, 2024Updated last year
- ☆15Jul 18, 2023Updated 2 years ago
- 「Chiselを始めたい人に読んで欲しい本」のサンプルコード用リポジトリ☆10Aug 26, 2021Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago