Alternatives and similar repositories for schoolRISCV

Users that are interested in schoolRISCV are comparing it to the libraries listed below

• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆152Updated last week
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆62Updated 2 years ago
• MIPSfpga / schoolMIPS
  CPU microarchitecture, step by step
  ☆205Updated 5 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆176Updated 2 months ago
• viktor-prutyanov / drec-fpga-intro
  Материалы для курсов по проектированию цифровых вычислительных систем
  ☆98Updated this week
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆55Updated 3 weeks ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆137Updated 2 weeks ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆43Updated 2 months ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆46Updated last month
• MPSU / exAPS
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆95Updated last year
• EDAMC / DigitalDesignSchool
  DigitalDesignSchool2022/23 repository
  ☆21Updated 3 years ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆21Updated 8 months ago
• MPSU / APS
  Методические материалы по разработке процессора архитектуры RISC-V
  ☆296Updated last week
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆76Updated last year
• DigitalDesignSchool / ce2020labs
  ChipEXPO 2020 Digital Design School Labs
  ☆37Updated 3 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Updated last year
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆39Updated last year
• MPSU / FPGA_pract
  Методические материалы курса "Практикум по ПЛИС"
  ☆40Updated 6 months ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆42Updated 6 years ago
• fpgacademy / DESim
  ☆45Updated 3 months ago
• stcmtk / fpga-webinar-2020
  ☆25Updated 5 years ago
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆13Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆457Updated this week
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• radigast / awesome-functional-verification
  list of links to resources related to functional verification
  ☆12Updated 2 years ago
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• yuri-panchul / yrv-plus
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆26Updated 2 years ago
• AntonovAlexander / activecore
  Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
  ☆32Updated 2 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago