Alternatives and similar repositories for schoolRISCV

Users that are interested in schoolRISCV are comparing it to the libraries listed below

• MIPSfpga / schoolMIPS

  View on GitHub
  CPU microarchitecture, step by step
  ☆206Nov 1, 2020Updated 5 years ago
• marsohod4you / Marsohod3GW

  View on GitHub
  Experiments with Marsohod3GW board with Gowin FPGA chip
  ☆17May 8, 2025Updated 9 months ago
• serge0699 / verif_elective_miet

  View on GitHub
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆16Aug 24, 2024Updated last year
• RomeoMe5 / DDLM

  View on GitHub
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆63Sep 15, 2023Updated 2 years ago
• riscv-tests-intro / riscv-tests-intro

  View on GitHub
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆47Nov 7, 2025Updated 3 months ago
• zhelnio / ddec

  View on GitHub
  Digital Design Express Course
  ☆19Apr 11, 2019Updated 6 years ago
• stcmtk / fpga-webinar-2020

  View on GitHub
  ☆25May 20, 2020Updated 5 years ago
• syntacore / scr1

  View on GitHub
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆962Nov 15, 2024Updated last year
• FPGA-Systems / fpga-awesome-list

  View on GitHub
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆177Oct 28, 2025Updated 3 months ago
• MPSU / MIRISCV

  View on GitHub
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Dec 5, 2024Updated last year
• RISCV-Alliance-Education / RISCV-Curricula

  View on GitHub
  Учебные материалы Альянса RISC-V
  ☆16Jun 30, 2025Updated 7 months ago
• viktor-prutyanov / drec-fpga-intro

  View on GitHub
  Материалы для курсов по проектированию цифровых вычислительных систем
  ☆98Jan 19, 2026Updated 3 weeks ago
• yuri-panchul / basics-graphics-music

  View on GitHub
  FPGA exercise for beginners
  ☆156Jan 19, 2026Updated 3 weeks ago
• chipdesignschool / basics-graphics-music

  View on GitHub
  FPGA exercise for beginners
  ☆43Oct 13, 2025Updated 4 months ago
• vlotnik / uvm_sin_cos_table

  View on GitHub
  Contains source code for sin/cos table verification using UVM
  ☆21Mar 9, 2021Updated 4 years ago
• MIPSfpga / mipsfpga-plus

  View on GitHub
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆112Jun 27, 2019Updated 6 years ago
• montedalrymple / yrv

  View on GitHub
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆19Jul 29, 2021Updated 4 years ago
• chipdesignschool / systemverilog-homework

  View on GitHub
  SystemVerilog language-oriented exercises
  ☆57Jan 30, 2026Updated 2 weeks ago
• OpenE2K / qemu-e2k

  View on GitHub
  QEMU With E2K User Support
  ☆52Apr 19, 2025Updated 9 months ago
• DigitalDesignSchool / ce2020labs

  View on GitHub
  ChipEXPO 2020 Digital Design School Labs
  ☆37Nov 11, 2022Updated 3 years ago
• nrot / WaveGen

  View on GitHub
  ☆11Jul 12, 2023Updated 2 years ago
• MPSU / exAPS

  View on GitHub
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆97Jan 27, 2024Updated 2 years ago
• MIPSfpga / digital-design-lab-manual

  View on GitHub
  Digital Design Labs
  ☆25Dec 21, 2018Updated 7 years ago
• MPSU / PCU-Verilog-labs

  View on GitHub
  Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
  ☆12Sep 4, 2023Updated 2 years ago
• stnolting / neorv32-riscof

  View on GitHub
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Feb 3, 2026Updated last week
• syntacore / scr1-sdk

  View on GitHub
  open-source SDKs for the SCR1 core
  ☆77Nov 15, 2024Updated last year
• MPSU / APS

  View on GitHub
  Методические материалы по разработке процессора архитектуры RISC-V
  ☆306Jan 14, 2026Updated last month
• stepanburmistrov / ROS2_robotV1

  View on GitHub
  ☆21Jun 3, 2025Updated 8 months ago
• AppLoidx / Web-Development-Cheats

  View on GitHub
  Articles and cheat sheets for web development
  ☆24May 3, 2023Updated 2 years ago
• westonb / sky130-analog

  View on GitHub
  Analog and power building blocks for sky130 pdk
  ☆22Mar 3, 2021Updated 4 years ago
• hurisson / pyuvm_primer

  View on GitHub
  Examples for using pyuvm
  ☆21Jun 5, 2024Updated last year
• zeeshanrafique23 / RV32I-Logisim

  View on GitHub
  RV32I single cycle simulation on open-source software Logisim.
  ☆21Oct 8, 2022Updated 3 years ago
• iDoka / book-mastering-fpgasic

  View on GitHub
  Mastering FPGASIC Book
  ☆18Oct 26, 2025Updated 3 months ago
• serge0699 / synth_school_verif_tasks

  View on GitHub
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆21Apr 11, 2025Updated 10 months ago
• cad-polito-it / ase_riscv_gem5_sim

  View on GitHub
  RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
  ☆30Nov 5, 2025Updated 3 months ago
• aws-samples / sha2-with-c-intrinsic

  View on GitHub
  An optimized sample code for SHA256 and SHA512 using C intrinsic
  ☆20May 31, 2020Updated 5 years ago
• chipsalliance / VeeR-ISS

  View on GitHub
  ☆151Oct 6, 2023Updated 2 years ago
• RClabiisc / I2SRV64-SS-v1

  View on GitHub
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Jun 22, 2024Updated last year
• tenstorrent / riscv_arch_tests

  View on GitHub
  Self checking RISC-V directed tests
  ☆119Jun 3, 2025Updated 8 months ago