Alternatives and similar repositories for PCU-Verilog-labs:

Users that are interested in PCU-Verilog-labs are comparing it to the libraries listed below

• iDoka / mastering-fpgasic-book
  Mastering FPGASIC Book
  ☆18Updated 3 years ago
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• MPSU / FPGA_pract
  Методические материалы курса "Практикум по ПЛИС"
  ☆28Updated this week
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆35Updated 2 months ago
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆32Updated 8 months ago
• nrot / WaveGen
  ☆11Updated last year
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆14Updated 3 months ago
• miet-mpsu-dsp / labs
  Лабораторные работы по ЦОС (python)
  ☆9Updated 11 months ago
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆38Updated last year
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆66Updated last week
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• esynr3z / adc-eval
  📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
  ☆19Updated last year
• stcmtk / fpga-webinar-2020
  ☆23Updated 4 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆23Updated 4 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆53Updated last year
• briansune / USB-PD-3.1-Verilog
  USB-PD-3.1-Verilog
  ☆12Updated 11 months ago
• yuri-panchul / yrv-plus
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆25Updated last year
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• TommyE79 / SITLINV-FPGA_Board
  Xlinix Kintex 7 based PCIE development board
  ☆22Updated last year
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated 4 months ago
• marsohod4you / Marsohod3GW
  Experiments with Marsohod3GW board with Gowin FPGA chip
  ☆12Updated 4 months ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated last month
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated 2 months ago
• NickolayTernovoy / risc-v_awesome_list
  ☆47Updated 3 years ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆41Updated 6 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆25Updated 5 years ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆40Updated 2 years ago
• esynr3z / pyhdlsim
  Example of Python and PyTest powered workflow for a HDL simulation
  ☆15Updated 4 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago