MPSU / PCU-Verilog-labs

Related projects ⓘ

Alternatives and complementary repositories for PCU-Verilog-labs

• iDoka / mastering-fpgasic-book
  Mastering FPGASIC Book
  ☆18Updated 2 years ago
• nrot / WaveGen
  ☆11Updated last year
• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 3 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆32Updated 2 months ago
• iDoka / eda-scripts
  Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
  ☆29Updated 4 months ago
• miet-mpsu-dsp / labs
  Лабораторные работы по ЦОС (python)
  ☆8Updated 7 months ago
• stcmtk / fpga-webinar-2020
  ☆23Updated 4 years ago
• MPSU / FPGA_pract
  Методические материалы курса "Практикум по ПЛИС"
  ☆17Updated 5 months ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated this week
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆48Updated 3 weeks ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• iDoka / asic-pinout-drawer
  Simple pin assignment generator for IC case
  ☆16Updated 7 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆41Updated 3 years ago
• NickolayTernovoy / risc-v_awesome_list
  ☆47Updated 3 years ago
• emb4fun / neorv32-examples
  Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.
  ☆15Updated last week
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆40Updated 5 years ago
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆11Updated 7 months ago
• ADA007 / FTDI_User_Area_Writer
  FTDI EEPROM User Area Writer For Xilinx JTAG Programmer
  ☆12Updated 10 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆26Updated 4 years ago
• aprgl / fx3
  USB interface for FPGA using a the Cypress FX3
  ☆13Updated 4 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 3 years ago
• montedalrymple / yrv
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆17Updated 3 years ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆23Updated 5 years ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 6 months ago
• iDoka / awesome-fpga-boards
  Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…
  ☆88Updated 3 years ago
• iDoka / GOST-28147-89
  Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
  ☆14Updated 8 months ago
• ChinaQMTECH / ZYNQ_BAJIE_BOARD
  ☆19Updated last year
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆20Updated 4 years ago