MPSU / PCU-Verilog-labs
Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
☆11Updated last year
Alternatives and similar repositories for PCU-Verilog-labs:
Users that are interested in PCU-Verilog-labs are comparing it to the libraries listed below
- Mastering FPGASIC Book☆18Updated 3 years ago
- Contains source code for sin/cos table verification using UVM☆20Updated 3 years ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆30Updated 6 months ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆35Updated 3 months ago
- Методические материалы курса "Практикум по ПЛИС"☆22Updated 7 months ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆12Updated last month
- Simple pin assignment generator for IC case☆17Updated 7 years ago
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆14Updated 10 months ago
- SystemVerilog language-oriented exercises☆58Updated 3 weeks ago
- Лабораторные работы по ЦОС (python)☆8Updated 8 months ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆22Updated 3 years ago
- ☆11Updated last year
- ☆23Updated 4 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆19Updated last year
- USB-PD-3.1-Verilog☆12Updated 8 months ago
- FPGA exercise for beginners☆95Updated this week
- Verilog (SystemVerilog) coding style☆40Updated 6 years ago
- VHDL PCIe Transceiver☆26Updated 4 years ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆42Updated 3 years ago
- QuSoC demo projects and template☆21Updated 7 months ago
- ULPI Link Wrapper (USB Phy Interface)☆25Updated 4 years ago
- Drawio => VHDL and Verilog☆51Updated last year
- Small footprint and configurable JESD204B core☆40Updated last week
- SDRAM controller for MIPSfpga+ system☆21Updated 4 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆21Updated last month
- human-in-the-loop HDL training tool☆33Updated 10 months ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆14Updated 2 months ago
- Cortex-M0 DesignStart Wrapper☆17Updated 5 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 3 years ago
- Digital Design Labs☆24Updated 6 years ago