MPSU / PCU-Verilog-labs
Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"
☆11Updated last year
Alternatives and similar repositories for PCU-Verilog-labs
Users that are interested in PCU-Verilog-labs are comparing it to the libraries listed below
Sorting:
- Методические материалы курса "Практикум по ПЛИС"☆28Updated last week
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- Mastering FPGASIC Book☆18Updated 3 years ago
- Лабораторные работы по ЦОС (python)☆9Updated 2 weeks ago
- ☆11Updated last year
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆17Updated 5 months ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆12Updated 8 months ago
- Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)☆32Updated 10 months ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆36Updated 3 months ago
- human-in-the-loop HDL training tool☆38Updated last year
- SDRAM controller for MIPSfpga+ system☆23Updated 4 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- ☆23Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆20Updated last year
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆18Updated 3 years ago
- Project and presentation for SpaceX Application☆14Updated 7 years ago
- Verilog (SystemVerilog) coding style☆41Updated 6 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- ☆43Updated 3 weeks ago
- Drawio => VHDL and Verilog☆55Updated last year
- Extensible FPGA control platform☆60Updated 2 years ago
- Digital Design Labs☆24Updated 6 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Updated 4 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated 3 weeks ago
- Small footprint and configurable JESD204B core☆42Updated 3 weeks ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- ULPI Link Wrapper (USB Phy Interface)☆26Updated 5 years ago