serge0699 / synth_school_verif_tasks
Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
☆15Updated 3 weeks ago
Alternatives and similar repositories for synth_school_verif_tasks:
Users that are interested in synth_school_verif_tasks are comparing it to the libraries listed below
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆35Updated 3 months ago
- SystemVerilog language-oriented exercises☆38Updated last month
- Методические материалы по разработке процессора архитектуры RISC-V☆162Updated this week
- DigitalDesignSchool2022/23 repository☆19Updated 2 years ago
- FPGA exercise for beginners☆32Updated this week
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆12Updated last month
- FPGA exercise for beginners☆95Updated this week
- SystemVerilog language-oriented exercises☆58Updated 3 weeks ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆157Updated 2 months ago
- Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ☆11Updated 7 months ago
- Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)☆93Updated 11 months ago
- ☆47Updated 3 years ago
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆54Updated last year
- CPU microarchitecture, step by step☆170Updated 2 years ago
- ChipEXPO 2020 Digital Design School Labs☆36Updated 2 years ago
- Static Timing Analysis Full Course☆46Updated 2 years ago
- Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)☆93Updated 2 months ago
- Control and Status Register map generator for HDL projects☆108Updated this week
- Учебные материалы Альянса RISC-V☆9Updated 2 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆131Updated this week
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆53Updated 9 months ago
- I2C slave Verilog Design and TestBench☆20Updated 5 years ago
- Verilog HDL files☆114Updated 7 months ago
- ☆130Updated 2 years ago
- ☆84Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆53Updated 2 years ago
- This repo provide an index of VLSI content creators and their materials☆140Updated 4 months ago
- Control and status register code generator toolchain☆112Updated 3 weeks ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- AHB3-Lite Interconnect☆83Updated 8 months ago