Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
☆25Mar 7, 2026Updated 5 months ago
Alternatives and similar repositories for synth_school_verif_tasks
Users that are interested in synth_school_verif_tasks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated last year
- Репозиторий канала Verification For All☆15May 27, 2026Updated 2 months ago
- FPGA exercise for beginners☆46Oct 13, 2025Updated 10 months ago
- Laboratory course on RISC-V Processor Development☆350Aug 10, 2026Updated last week
- human-in-the-loop HDL training tool☆44Feb 27, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- SystemVerilog language-oriented exercises☆61Jul 8, 2026Updated last month
- Открытое RISC-V процессорное ядро MIRISCV для образо вательных целей☆32Dec 5, 2024Updated last year
- Методические материалы курса "Практикум по ПЛИС"☆51May 29, 2026Updated 2 months ago
- Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ☆12Feb 4, 2025Updated last year
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆53May 16, 2026Updated 3 months ago
- ChipEXPO 2020 Digital Design School Labs☆39Nov 11, 2022Updated 3 years ago
- SystemVerilog language-oriented exercises☆176Jul 8, 2026Updated last month
- DigitalDesignSchool2022/23 repository☆21Dec 2, 2022Updated 3 years ago
- FPGA exercise for beginners☆186Jul 27, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- ☆19Dec 20, 2025Updated 8 months ago
- Audio filtering with pyfda and cocotb☆13Sep 24, 2020Updated 5 years ago
- CPU microarchitecture, step by step☆196Jun 26, 2022Updated 4 years ago
- ☆11Jul 12, 2023Updated 3 years ago
- ☆15Dec 18, 2022Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 6 months ago
- Karnaugh Interactive Extendable ASIC Simulation Board AKA Karnix ASB-254☆19May 19, 2024Updated 2 years ago
- IPDBG☆13Aug 22, 2025Updated 11 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- TangPrimer-20K-example project☆243Jun 6, 2026Updated 2 months ago
- list of links to resources related to functional verification☆12Sep 10, 2023Updated 2 years ago
- ☆47Apr 1, 2026Updated 4 months ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 6 years ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆12Sep 4, 2023Updated 2 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- A PCB based business card using open hardware and free software☆13Sep 10, 2024Updated last year
- Sources for studying STM32 microcontrollers.☆32May 29, 2025Updated last year
- ☆16Jan 9, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- UVM-SystemC reference implementation☆20Apr 8, 2026Updated 4 months ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 11 months ago
- ☆19Feb 27, 2023Updated 3 years ago
- An adapter board with pin headers for low-pin count (LPC) FPGA Mezzanine Cards (FMC).☆12Nov 2, 2020Updated 5 years ago
- ☆15Apr 14, 2023Updated 3 years ago
- TCL scripts for FPGA (Xilinx)☆36Jul 5, 2022Updated 4 years ago
- uRV RISC-V core☆19Sep 29, 2015Updated 10 years ago