Alternatives and similar repositories for RISCV-Curricula

Users that are interested in RISCV-Curricula are comparing it to the libraries listed below

• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆55Updated last month
• MPSU / MIRISCV
  Открытое RISC-V процессорное ядро MIRISCV для образовательных целей
  ☆23Updated last year
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆46Updated 2 months ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆21Updated 9 months ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆154Updated this week
• MPSU / FPGA_pract
  Методические материалы курса "Практикум по ПЛИС"
  ☆40Updated 7 months ago
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆43Updated 3 months ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆62Updated 2 years ago
• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆186Updated 3 years ago
• EDAMC / DigitalDesignSchool
  DigitalDesignSchool2022/23 repository
  ☆21Updated 3 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆176Updated 2 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆138Updated last month
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆40Updated last year
• yuri-panchul / yrv-plus
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆26Updated 2 years ago
• MPSU / exAPS
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆95Updated last year
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆13Updated last year
• MPSU / APS
  Методические материалы по разработке процессора архитектуры RISC-V
  ☆301Updated last week
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆76Updated last year
• fpgacademy / DESim
  ☆46Updated 3 months ago
• DigitalDesignSchool / ce2020labs
  ChipEXPO 2020 Digital Design School Labs
  ☆37Updated 3 years ago
• marsohod4you / jtag_hw_mbftdi_blaster
  ☆37Updated 4 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆26Updated 6 months ago
• radigast / awesome-functional-verification
  list of links to resources related to functional verification
  ☆12Updated 2 years ago
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago
• lushaylabs / tangnano9k-series-examples
  Examples for the Lushay Labs tang nano 9k series
  ☆126Updated last year
• iDoka / book-mastering-fpgasic
  Mastering FPGASIC Book
  ☆18Updated 2 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated last month
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆249Updated 3 months ago
• HDLForBeginners / Examples
  ☆115Updated 2 years ago