MIPSfpga / schoolMIPSView external linksLinks
CPU microarchitecture, step by step
☆206Nov 1, 2020Updated 5 years ago
Alternatives and similar repositories for schoolMIPS
Users that are interested in schoolMIPS are comparing it to the libraries listed below
Sorting:
- CPU microarchitecture, step by step☆186Jun 26, 2022Updated 3 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆112Jun 27, 2019Updated 6 years ago
- Digital Design Labs☆25Dec 21, 2018Updated 7 years ago
- ☆25May 20, 2020Updated 5 years ago
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆63Sep 15, 2023Updated 2 years ago
- Материалы для курсов по проектированию цифровых вычислительных систем☆98Jan 19, 2026Updated 3 weeks ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 6 years ago
- A collection of SPI related cores☆21Nov 12, 2024Updated last year
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆417Updated this week
- MIPS CPU implemented in Verilog☆642Oct 3, 2017Updated 8 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆962Nov 15, 2024Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- ChipEXPO 2020 Digital Design School Labs☆37Nov 11, 2022Updated 3 years ago
- A small RISC-V core (SystemVerilog)☆34Aug 26, 2019Updated 6 years ago
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 8 years ago
- MACS RTOS kernel repository☆34Jun 21, 2021Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆58Dec 31, 2019Updated 6 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,945Jun 27, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,008Dec 15, 2025Updated last month
- Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs☆358Jun 11, 2022Updated 3 years ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆177Oct 28, 2025Updated 3 months ago
- A small, light weight, RISC CPU soft core☆1,507Dec 8, 2025Updated 2 months ago
- ☆41Apr 4, 2021Updated 4 years ago
- SPI core☆14Oct 25, 2019Updated 6 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 9 years ago
- SERV - The SErial RISC-V CPU☆1,751Updated this week
- 奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）☆130Nov 13, 2019Updated 6 years ago
- Port of the original radio-86rk_SDRAM Altera DE1 code to the WXEDA board☆16Mar 13, 2015Updated 10 years ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,489Jan 7, 2026Updated last month
- Verilog implementation of a RISC-V core☆135Oct 11, 2018Updated 7 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆23Dec 5, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,183May 26, 2025Updated 8 months ago
- Common SystemVerilog components☆706Feb 6, 2026Updated last week
- Various HDL (Verilog) IP Cores☆873Jul 1, 2021Updated 4 years ago
- All digital AM radio receiver implemented on the stm32l4-discovery board.☆21May 19, 2021Updated 4 years ago
- Mastering FPGASIC Book☆18Oct 26, 2025Updated 3 months ago
- RISC-V CPU Core (RV32IM)☆1,640Sep 18, 2021Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Jan 27, 2026Updated 2 weeks ago
- Multi-platform nightly builds of open source FPGA tools☆301Nov 3, 2021Updated 4 years ago