Alternatives and similar repositories for schoolMIPS

Users that are interested in schoolMIPS are comparing it to the libraries listed below

• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆181Updated 3 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆109Updated 6 years ago
• syntacore / scr1-sdk
  open-source SDKs for the SCR1 core
  ☆74Updated 8 months ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆121Updated last week
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆123Updated 6 years ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆193Updated 3 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆363Updated last month
• ejrh / cpu
  A very primitive but hopefully self-educational CPU in Verilog
  ☆145Updated 10 years ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆101Updated last month
• ZipCPU / vgasim
  A Video display simulator
  ☆171Updated 2 months ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆90Updated 7 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆308Updated last year
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 3 weeks ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆278Updated 11 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆168Updated 4 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆166Updated 8 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 4 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆241Updated 9 months ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆153Updated 7 years ago
• subbdue / systemverilog.io
  Code used in
  ☆193Updated 8 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆139Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• jamieiles / uart
  Verilog UART
  ☆177Updated 12 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆265Updated 3 months ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆42Updated 3 weeks ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆176Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆321Updated 7 months ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆171Updated 9 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆121Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago