yuri-panchul / basics-graphics-musicLinks
FPGA exercise for beginners
☆129Updated this week
Alternatives and similar repositories for basics-graphics-music
Users that are interested in basics-graphics-music are comparing it to the libraries listed below
Sorting:
- SystemVerilog language-oriented exercises☆116Updated 3 months ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆169Updated 10 months ago
- CPU microarchitecture, step by step☆181Updated 3 years ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆43Updated 2 months ago
- SystemVerilog language-oriented exercises☆49Updated 3 months ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆22Updated 5 months ago
- ☆48Updated 3 years ago
- human-in-the-loop HDL training tool☆38Updated last year
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆60Updated 2 years ago
- ☆44Updated last week
- ☆106Updated 2 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆20Updated 10 months ago
- open-source SDKs for the SCR1 core☆75Updated 10 months ago
- FuseSoC standard core library☆147Updated 4 months ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆180Updated last year
- A simple, basic, formally verified UART controller☆311Updated last year
- Drawio => VHDL and Verilog☆57Updated last year
- 10Gb Ethernet Switch☆231Updated last week
- Example LED blinking project for your FPGA dev board of choice☆184Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆96Updated this week
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆149Updated 4 years ago
- CPU microarchitecture, step by step☆202Updated 4 years ago
- Arduino compatible Risc-V Based SOC☆156Updated last year
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- ChipEXPO 2020 Digital Design School Labs☆37Updated 2 years ago
- Communication framework for RTL simulation and emulation.☆301Updated this week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆415Updated last week
- VHDL library 4 FPGAs☆181Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆13Updated last year