FPGA exercise for beginners
☆204Oct 30, 2026Updated this week
Alternatives and similar repositories for basics-graphics-music
Users that are interested in basics-graphics-music are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog language-oriented exercises☆197Jul 8, 2026Updated 3 months ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆54Sep 20, 2026Updated last month
- Laboratory course on RISC-V Processor Development☆360Updated this week
- SystemVerilog language-oriented exercises☆77Jul 8, 2026Updated 3 months ago
- Методические материалы курса "Практикум по ПЛИС"☆50May 29, 2026Updated 5 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Karnaugh Interactive Extendable ASIC Simulation Board AKA Karnix ASB-254☆19Sep 6, 2026Updated last month
- FPGA exercise for beginners☆62Oct 10, 2026Updated 3 weeks ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆19Aug 24, 2024Updated 2 years ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆27Updated this week
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- human-in-the-loop HDL training tool☆44Feb 27, 2024Updated 2 years ago
- SystemVerilog microarchitecture challenge for AI No.2. Adding the flow control.☆29Sep 4, 2025Updated last year
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 3 years ago
- A tool for creating HDL-Schematics☆10Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CPU microarchitecture, step by step☆200Jun 26, 2022Updated 4 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆28Jul 31, 2023Updated 3 years ago
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 5 years ago
- Исходные коды к Цифровой синтез: RISC-V☆15Sep 9, 2024Updated 2 years ago
- ☆15Apr 14, 2023Updated 3 years ago
- ☆14Apr 29, 2024Updated 2 years ago
- Experiments with Marsohod3GW board with Gowin FPGA chip☆20May 8, 2025Updated last year
- ☆21Oct 8, 2026Updated 3 weeks ago
- ☆10Nov 2, 2023Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Полезные ресурсы по тематике FPGA / ПЛИС☆186Oct 28, 2025Updated last year
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- DigitalDesignSchool2022/23 repository☆21Dec 2, 2022Updated 3 years ago
- A tool for modeling FSMs by VHDL or Verilog☆15Updated this week
- TangNano-9K-example project☆368Apr 8, 2024Updated 2 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆657Updated this week
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆34Dec 5, 2024Updated last year
- list of links to resources related to functional verification☆12Sep 10, 2023Updated 3 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆67Sep 15, 2023Updated 3 years ago
- ChipEXPO 2020 Digital Design School Labs☆39Nov 11, 2022Updated 3 years ago
- ☆27Aug 4, 2024Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆36Oct 15, 2024Updated 2 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated last year