yuri-panchul / systemverilog-homework
SystemVerilog language-oriented exercises
☆77Updated 3 weeks ago
Alternatives and similar repositories for systemverilog-homework:
Users that are interested in systemverilog-homework are comparing it to the libraries listed below
- FPGA exercise for beginners☆107Updated 3 weeks ago
- Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем☆19Updated 2 weeks ago
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆35Updated 3 months ago
- Полезные ресурсы по тематике FPGA / ПЛИС☆161Updated 5 months ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆15Updated 4 months ago
- ☆47Updated 3 years ago
- Contains source code for sin/cos table verification using UVM☆20Updated 4 years ago
- CPU microarchitecture, step by step☆176Updated 2 years ago
- Control and Status Register map generator for HDL projects☆116Updated this week
- Static Timing Analysis Full Course☆52Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- SystemVerilog language-oriented exercises☆44Updated 3 weeks ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆18Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- A small RISC-V core (SystemVerilog)☆32Updated 5 years ago
- Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)☆56Updated last year
- Open source ISS and logic RISC-V 32 bit project☆50Updated last week
- FPGA exercise for beginners☆35Updated 2 months ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 5 months ago
- human-in-the-loop HDL training tool☆38Updated last year
- Pipelined RISC-V RV32I Core in Verilog☆38Updated 2 years ago
- ☆42Updated this week
- Drawio => VHDL and Verilog☆54Updated last year
- Учебные материалы Альянса RISC-V☆13Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- ☆64Updated 3 years ago
- ☆92Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 11 months ago