Alternatives and similar repositories for drec-fpga-intro

Users that are interested in drec-fpga-intro are comparing it to the libraries listed below

• zhelnio / schoolRISCV
  CPU microarchitecture, step by step
  ☆185Updated 3 years ago
• RomeoMe5 / DDLM
  Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
  ☆62Updated 2 years ago
• MPSU / APS
  Методические материалы по разработке процессора архитектуры RISC-V
  ☆296Updated last week
• MPSU / exAPS
  Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)
  ☆95Updated last year
• chipdesignschool / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆54Updated 2 weeks ago
• EDAMC / DigitalDesignSchool
  DigitalDesignSchool2022/23 repository
  ☆21Updated 3 years ago
• chipdesignschool / basics-graphics-music
  FPGA exercise for beginners
  ☆43Updated 2 months ago
• NickolayTernovoy / risc-v_awesome_list
  ☆48Updated 4 years ago
• DigitalDesignSchool / ce2020labs
  ChipEXPO 2020 Digital Design School Labs
  ☆37Updated 3 years ago
• stcmtk / fpga-webinar-2020
  ☆25Updated 5 years ago
• yuri-panchul / basics-graphics-music
  FPGA exercise for beginners
  ☆152Updated this week
• edosedgar / stm32f0_ARM
  Materials for the course "Embedded programming on STM32"
  ☆178Updated 2 years ago
• FPGA-Systems / fpga-awesome-list
  Полезные ресурсы по тематике FPGA / ПЛИС
  ☆176Updated 2 months ago
• MPSU / FPGA_pract
  Методические материалы курса "Практикум по ПЛИС"
  ☆40Updated 6 months ago
• MIPSfpga / schoolMIPS
  CPU microarchitecture, step by step
  ☆205Updated 5 years ago
• riscv-tests-intro / riscv-tests-intro
  Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"
  ☆46Updated last month
• zhelnio / ddec
  Digital Design Express Course
  ☆19Updated 6 years ago
• serge0699 / synth_school_verif_tasks
  Репозиторий заданий и примеров направления функциональной верификации Школы синтеза цифровых схем
  ☆21Updated 8 months ago
• yuri-panchul / yrv-plus
  Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
  ☆26Updated 2 years ago
• johan92 / verilog-coding-style
  Verilog (SystemVerilog) coding style
  ☆42Updated 6 years ago
• ef-end-y / RiverRaidFPGA
  River Raid game on FPGA
  ☆25Updated 9 years ago
• Korogodin / NSLReport
  NavSysLab LaTeX report project for GOST 7.0.11, 7.32, 2.105 documents
  ☆48Updated last year
• iDoka / book-mastering-fpgasic
  Mastering FPGASIC Book
  ☆18Updated 2 months ago
• RISCV-Alliance-Education / RISCV-Curricula
  Учебные материалы Альянса RISC-V
  ☆14Updated 6 months ago
• smirnovalnik / microprocessor-units-course
  Микропроцессорные устройства
  ☆13Updated 7 months ago
• yuri-panchul / systemverilog-homework
  SystemVerilog language-oriented exercises
  ☆136Updated last week
• MIPT-ILab / ca-lectures
  Lectures on Computer Architecture
  ☆13Updated 3 years ago
• MIPSfpga / digital-design-lab-manual
  Digital Design Labs
  ☆25Updated 7 years ago
• FPGA-InsideOut / hdlgadgets
  human-in-the-loop HDL training tool
  ☆39Updated last year
• dee3mon / altium-methodic
  Materials for students
  ☆20Updated 3 weeks ago