Alternatives and similar repositories for cmurphi

Users that are interested in cmurphi are comparing it to the libraries listed below

• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆13Updated 3 years ago
• theoxo / coherence
  MSI cache coherence protocol written/verified in Murphi
  ☆8Updated 7 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated 10 months ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆22Updated 4 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆22Updated last year
• ymanerka / ccicheck
  ☆9Updated 9 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆72Updated 4 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated last week
• efeslab / asplos22-hardware-debugging-artifact
  ☆12Updated 11 months ago
• iscas-tis / CHA
  ☆19Updated 10 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆51Updated this week
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• ymanerka / rtlcheck
  RTLCheck
  ☆21Updated 6 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆46Updated last week
• yaohsiaopid / rtl2uspec
  ☆11Updated last year
• Errare-humanum-est / ProtoGen
  Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…
  ☆16Updated 3 years ago
• UCLA-SEAL / HeteroGen
  HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
  ☆17Updated 7 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆67Updated this week
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆12Updated 4 years ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 5 years ago
• amahzoon / genmul
  ☆16Updated 4 years ago
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆38Updated 4 months ago
• sterin / super-prove-build
  ☆13Updated 4 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆22Updated 3 months ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• gpt4rtl / AutoSVA2
  ☆15Updated last year