veripool / dinotrace
Simulation VCD waveform viewer, using old Motif UI
☆25Updated last year
Related projects ⓘ
Alternatives and complementary repositories for dinotrace
- IRSIM switch-level simulator for digital circuits☆30Updated 6 months ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated last year
- A bit-serial CPU☆18Updated 5 years ago
- A Verilog Synthesis Regression Test☆34Updated 8 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆20Updated 3 years ago
- 64-bit MISC Architecture CPU☆11Updated 7 years ago
- Digital Circuit rendering engine☆35Updated last year
- Implementation of a circular queue in hardware using verilog.☆16Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆54Updated last month
- Open Processor Architecture☆26Updated 8 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- CMod-S6 SoC☆36Updated 6 years ago
- OpenFPGA☆33Updated 6 years ago
- S3GA: a simple scalable serial FPGA☆10Updated last year
- A padring generator for ASICs☆22Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- Export netlists from Yosys to DigitalJS☆46Updated 10 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- FuseSoc Verification Automation☆21Updated 2 years ago
- ☆10Updated 5 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago