veripool / dinotraceLinks
Simulation VCD waveform viewer, using old Motif UI
☆26Updated 2 years ago
Alternatives and similar repositories for dinotrace
Users that are interested in dinotrace are comparing it to the libraries listed below
Sorting:
- USB 1.1 Device IP Core☆21Updated 7 years ago
- A bit-serial CPU☆19Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last week
- IRSIM switch-level simulator for digital circuits☆34Updated 3 months ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆28Updated 2 years ago
- Reusable Verilog 2005 components for FPGA designs☆45Updated 4 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Digital Circuit rendering engine☆39Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS☆37Updated 3 years ago
- Export netlists from Yosys to DigitalJS☆51Updated last year
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆28Updated 5 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- Virtual Development Board☆60Updated 3 years ago
- Utilities for working with a Wishbone bus in an embedded device☆44Updated 2 weeks ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Web-based HDL diagramming tool☆79Updated 2 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Library of FPGA architectures☆23Updated 3 weeks ago
- HDMI Expansion Modules compatible with the Pmod standard☆11Updated 7 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- ☆10Updated 5 years ago