Alternatives and similar repositories for dinotrace

Users that are interested in dinotrace are comparing it to the libraries listed below

• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆19Updated 6 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• steveicarus / simbus
  Icarus SIMBUS
  ☆20Updated 6 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 4 years ago
• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆55Updated 2 weeks ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆45Updated 3 years ago
• litex-hub / wishbone-utils
  Utilities for working with a Wishbone bus in an embedded device
  ☆47Updated 4 months ago
• knielsen / ice40_viewer
  ☆61Updated 2 years ago
• FPGAwars / toolchain-icestorm
  Icestorm, Arachne-pnr and Yosys pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
  ☆38Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆17Updated 6 years ago
• olofk / vidbo
  Virtual Development Board
  ☆64Updated 4 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 5 months ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆34Updated 2 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated this week
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆65Updated 7 months ago
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆20Updated 12 years ago
• ironsteel / nes_ecp5
  NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board
  ☆38Updated 3 years ago
• OLIMEX / iCE40HX8K-EVB
  iCE40HX8K development board with SRAM and bus for fast ADC, DAC, IOs
  ☆39Updated last year
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• hamsternz / emulate-risc-v
  A very simple RISC-V ISA emulator.
  ☆39Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated 3 weeks ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 2 months ago
• mattvenn / logo-to-gds2
  ☆18Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆49Updated 3 weeks ago