veripool / dinotraceLinks
Simulation VCD waveform viewer, using old Motif UI
☆26Updated 2 years ago
Alternatives and similar repositories for dinotrace
Users that are interested in dinotrace are comparing it to the libraries listed below
Sorting:
- Implementation of a circular queue in hardware using verilog.☆17Updated 6 years ago
- A bit-serial CPU☆19Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- ☆10Updated 5 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆28Updated 2 weeks ago
- IRSIM switch-level simulator for digital circuits☆34Updated 2 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 6 months ago
- A Verilog Synthesis Regression Test☆37Updated last year
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- PicoRV☆44Updated 5 years ago
- Open Processor Architecture☆26Updated 9 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Co-simulation and behavioural verification with VHDL, C/C++ and Python/m☆13Updated last week
- 5-stage RISC-V CPU, originally developed for RISCBoy☆27Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Digital Circuit rendering engine☆39Updated last year
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- RISC-V processor☆31Updated 3 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 4 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆22Updated 3 years ago
- ☆22Updated last month
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- S3GA: a simple scalable serial FPGA☆10Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 5 months ago