IamFlea / AdderCircuitGeneratorLinks
This script generates and analyzes prefix tree adders.
☆39Updated 4 years ago
Alternatives and similar repositories for AdderCircuitGenerator
Users that are interested in AdderCircuitGenerator are comparing it to the libraries listed below
Sorting:
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- ☆82Updated last year
- An integrated CGRA design framework☆91Updated 10 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- ☆87Updated last year
- ☆19Updated 8 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆18Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆91Updated 9 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- A DSL for Systolic Arrays☆83Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆82Updated 2 months ago
- ☆29Updated 8 years ago
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- ☆29Updated 6 years ago
- ☆22Updated 2 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆41Updated 3 months ago
- CGRA framework with vectorization support.☆43Updated 2 weeks ago
- Next generation CGRA generator☆118Updated last week
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 6 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last month
- This is a tutorial on standard digital design flow☆83Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago