Alternatives and similar repositories for AdderCircuitGenerator

Users that are interested in AdderCircuitGenerator are comparing it to the libraries listed below

• arcade-lab / tia-infrastructure
  ☆19Updated 7 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 4 months ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆22Updated 3 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆44Updated last year
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆51Updated last week
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆89Updated 3 months ago
• lana555 / dynamatic
  ☆86Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆63Updated 5 years ago
• Deepak42074 / Sky130-RTL-Design-And-Synthesis-Using-Verilog
  ☆13Updated 3 years ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆27Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 3 weeks ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• Ams0x57 / Digital_Adders_Verilog
  32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…
  ☆24Updated 7 years ago
• ucb-bar / sha3
  ☆81Updated last year
• hngenc / systolic-array
  A DSL for Systolic Arrays
  ☆79Updated 6 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆31Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 7 months ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆76Updated 9 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated last week