yan-david-1 / Tricks-about-analog-RF-IC-designLinks
☆61Updated last year
Alternatives and similar repositories for Tricks-about-analog-RF-IC-design
Users that are interested in Tricks-about-analog-RF-IC-design are comparing it to the libraries listed below
Sorting:
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆62Updated 7 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆205Updated last month
- ☆147Updated 3 weeks ago
- Some useful documents of Synopsys☆76Updated 3 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- AXI协议规范中文翻译版☆153Updated 3 years ago
- ☆70Updated 4 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆51Updated 11 months ago
- AXI总线连接器☆100Updated 5 years ago
- Pipeline FFT Implementation in Verilog HDL☆122Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆116Updated 12 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆169Updated 8 months ago
- ☆67Updated 9 years ago
- ☆50Updated last month
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆52Updated 3 years ago
- Vivado诸多IP，包括图像处理等☆209Updated 11 months ago
- A collection of license features from a varity of EDA vendors☆69Updated last year
- Open IP in Hardware Description Language.☆24Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- 基于FPGA的三速以太网UDP协议栈设计☆27Updated last year
- this repository is vim cfg for verilog.☆49Updated 11 months ago
- ☆221Updated 4 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆69Updated 2 years ago
- Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。☆148Updated 6 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 4 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆202Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆121Updated 2 years ago