Alternatives and similar repositories for Tricks-about-analog-RF-IC-design

Users that are interested in Tricks-about-analog-RF-IC-design are comparing it to the libraries listed below

• zlijingtao / Digital-Calibration-of-SAR-ADC
  Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
  ☆67Updated 7 years ago
• bmurmann / ADC-survey
  ADC Performance Survey (ISSCC & VLSI Circuit Symposium)
  ☆241Updated 4 months ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆153Updated last month
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆93Updated 4 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆171Updated 3 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆84Updated 4 months ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆186Updated last year
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆54Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆113Updated 3 years ago
• ColsonZhang / VerilogA-Wave-Generator
  The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…
  ☆54Updated 3 weeks ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• VardhanSuroshi / Memory-Design-And-Testing
  The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
  ☆52Updated last year
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆153Updated 6 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆81Updated 3 years ago
• RongyeL / EasyAXI
  ☆83Updated last week
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆75Updated 4 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆235Updated 2 years ago
• ForrestBlue / cortexm0ds
  ☆73Updated 9 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆80Updated 2 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• ic7x24 / verilog-mini-demo
  Verilog极简教程
  ☆36Updated 6 years ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆51Updated 11 months ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆108Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆99Updated last year
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆69Updated last year
• loykylewong / FPGA-Application-Development-and-Simulation
  《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
  ☆133Updated last week
• Starrynightzyq / Delta-Sigma-Modulator
  Delta-Sigma modulator (DSM) for fractional phase locked loop.
  ☆33Updated 4 years ago