yan-david-1 / Tricks-about-analog-RF-IC-designLinks
☆64Updated last year
Alternatives and similar repositories for Tricks-about-analog-RF-IC-design
Users that are interested in Tricks-about-analog-RF-IC-design are comparing it to the libraries listed below
Sorting:
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆67Updated 7 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆214Updated last month
- ☆149Updated 2 weeks ago
- Some useful documents of Synopsys☆85Updated 3 years ago
- AXI协议规范中文翻译版☆163Updated 3 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆175Updated 10 months ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆54Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- 《FPGA应用开发和仿真》(机械工业出版社2018年第1版 ISBN:9787111582786)的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated 3 weeks ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆67Updated last year
- ☆69Updated 2 weeks ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆110Updated 3 years ago
- AXI总线连接器☆104Updated 5 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- Pipeline FFT Implementation in Verilog HDL☆132Updated 6 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆208Updated 2 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆57Updated last year
- A collection of license features from a varity of EDA vendors☆74Updated last month
- this repository is vim cfg for verilog.☆50Updated last year
- ☆69Updated 9 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆73Updated 4 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆71Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Vivado诸多IP,包括图像处理等☆229Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆123Updated 3 years ago
- ☆23Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆76Updated 3 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆97Updated 3 years ago