yan-david-1 / Tricks-about-analog-RF-IC-designLinks
☆63Updated last year
Alternatives and similar repositories for Tricks-about-analog-RF-IC-design
Users that are interested in Tricks-about-analog-RF-IC-design are comparing it to the libraries listed below
Sorting:
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆65Updated 7 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆210Updated 2 weeks ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆173Updated 9 months ago
- Some useful documents of Synopsys☆82Updated 3 years ago
- ☆149Updated 2 weeks ago
- FFT implement by verilog_测试验证已通过☆60Updated 8 years ago
- AXI协议规范中文翻译版☆162Updated 3 years ago
- The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuct…☆54Updated 3 years ago
- A collection of license features from a varity of EDA vendors☆74Updated 3 weeks ago
- Cortex M0 based SoC☆74Updated 3 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆55Updated last year
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆33Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆72Updated 2 years ago
- this repository is vim cfg for verilog.☆50Updated last year
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆119Updated 12 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆36Updated last year
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- AXI总线连接器☆103Updated 5 years ago
- ☆68Updated 9 years ago
- ☆58Updated last week
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆66Updated last year
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆108Updated 2 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆30Updated 4 years ago
- 我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆94Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆75Updated 3 years ago
- 《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).☆132Updated this week
- ☆23Updated 5 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆81Updated 4 years ago