Alternatives and similar repositories for VirtuosoToolboxMatlab

Users that are interested in VirtuosoToolboxMatlab are comparing it to the libraries listed below

• KenKundert / psf_utils
  Read Spectre PSF files
  ☆64Updated last week
• muhammadaldacher / Analog-Design-of-Bootstrapped-Switch
  This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…
  ☆11Updated 5 years ago
• fengqzHD / gmIdNeoKit
  Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
  ☆46Updated 5 years ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 7 years ago
• medwatt / gmid
  Python script for generating lookup tables for the gm/ID design methodology and much more ...
  ☆89Updated last month
• dreoilin / pygmid
  A python3 gm/ID starter kit
  ☆48Updated 9 months ago
• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆77Updated 8 years ago
• sandarm-1 / Gm_over_Id_methodology
  Gm over Id methodology
  ☆23Updated 2 years ago
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆14Updated last year
• ananthchellappa / SKILL
  Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.
  ☆45Updated this week
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆54Updated this week
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆67Updated last year
• bmurmann / Book-on-gm-ID-design
  Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
  ☆138Updated this week
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆31Updated 3 years ago
• cdsdm / cdsdm
  Cadence Virtuoso Design Management System
  ☆34Updated 2 years ago
• richard259 / serdespy
  Python library for SerDes modelling
  ☆69Updated 10 months ago
• bmurmann / Ngspice-on-Colab
  Sandbox for experimenting with Ngspice and open PDKs in Google Colab
  ☆21Updated last year
• cascode-labs / virtue
  A Python and SKILL Framework for Cadence Virtuoso
  ☆39Updated last year
• wulffern / aic2023
  Advanced integrated circuits 2023
  ☆30Updated last year
• ucb-art / bag
  BAG framework
  ☆29Updated 5 months ago
• muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …
  ☆28Updated 6 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• AbdelrahmanHassanMuhammed / Analog-IC-Design-Problems
  Solve one design problem each day for a month
  ☆43Updated 2 years ago
• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆23Updated 2 years ago
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆28Updated 4 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆69Updated 4 years ago
• ebecheto / Skill
  my cadence/virtuoso/icfb skill functions develloped over the years
  ☆131Updated last month
• siddhantladdha / analog_daddy
  This library is an attempt to make transistor sizing for Analog design less painful.
  ☆18Updated last year