Alternatives and similar repositories for VirtuosoToolboxMatlab

Users that are interested in VirtuosoToolboxMatlab are comparing it to the libraries listed below

• KenKundert / psf_utils
  Read Spectre PSF files
  ☆65Updated last week
• medwatt / gmid
  Python script for generating lookup tables for the gm/ID design methodology and much more ...
  ☆95Updated 3 months ago
• fengqzHD / gmIdNeoKit
  Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
  ☆47Updated 5 years ago
• bmurmann / Book-on-gm-ID-design
  Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"
  ☆156Updated this week
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆71Updated 2 years ago
• muhammadaldacher / Analog-Design-of-Bootstrapped-Switch
  This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…
  ☆11Updated 6 years ago
• bmurmann / EE628
  EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)
  ☆162Updated last week
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• ucb-art / BAG_framework
  ☆148Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆56Updated this week
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆168Updated 8 months ago
• richard259 / serdespy
  Python library for SerDes modelling
  ☆72Updated last year
• unihd-cag / skillbridge
  A seamless python to Cadence Virtuoso Skill interface
  ☆224Updated 5 months ago
• ncsu-eda / FreePDK3
  ☆157Updated 3 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆58Updated 5 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆73Updated 3 years ago
• ucb-art / bag
  BAG framework
  ☆30Updated 7 months ago
• muhammadaldacher / Analog-Design-of-1.5-bit-Pipeline-ADC-And-Boosted-OpAmp
  This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.
  ☆32Updated 3 years ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆54Updated 8 years ago
• bmurmann / ADC-survey
  ADC Performance Survey (ISSCC & VLSI Circuit Symposium)
  ☆208Updated 2 weeks ago
• cdsgit / cdsgit
  Cadence Virtuoso Git Integration written in SKILL++
  ☆158Updated 2 years ago
• phonon / sar-adc-metastability
  Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"
  ☆11Updated 3 years ago
• dreoilin / pygmid
  A python3 gm/ID starter kit
  ☆51Updated 11 months ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆186Updated 2 months ago
• sscs-ose / sscs-chipathon-2024
  ☆84Updated 6 months ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆78Updated last week
• muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …
  ☆31Updated 6 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆37Updated 5 years ago
• ChrisZonghaoLi / gm_id_gf180mcu
  This repo contains introduction of gm/id method and its application to some OTA design examples.
  ☆18Updated last year