Ashwin-op / CMOS_Circuit_Generator
Converting Boolean expressions to CMOS Circuits
☆9Updated 4 years ago
Alternatives and similar repositories for CMOS_Circuit_Generator:
Users that are interested in CMOS_Circuit_Generator are comparing it to the libraries listed below
- Graph your gate-level verilog code as a directed graph!☆16Updated 4 years ago
- All the projects and assignments done as part of VLSI course.☆18Updated 4 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆16Updated 4 years ago
- RISC V core implementation using Verilog.☆26Updated 3 years ago
- This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…☆16Updated 3 years ago
- A SoC for DOOM☆16Updated 3 years ago
- NVDLA modifications for GreenSocs models/simple_cpu (https://git.greensocs.com/models/simple_cpu)☆18Updated 6 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 10 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆45Updated 5 months ago
- A small Unity AI game built with ML-agents v0.5☆14Updated 6 years ago
- A 32-Bit RISC Processor implemented on Logisim along with a python based assembler.☆17Updated 7 years ago
- Implementation of the TIS-100 Tessellated Intelligence System.☆10Updated 8 years ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆29Updated 3 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆17Updated 5 years ago
- Human Resource Machine - CPU Design #HRM☆75Updated 3 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Updated last month
- RV32I single cycle simulation on open-source software Logisim.☆17Updated 2 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆29Updated this week
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆11Updated 3 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆85Updated 5 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆16Updated 2 years ago
- Automatic Test Pattern Generation using PODEM algorithm☆13Updated 10 years ago
- An unofficial community "fork" of the M3D software provided for use with the M3D Micro and M3D Pro printers.☆13Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- Hastlayer-compatible arithmetics package. Includes the .NET implementation of the unum and posit number formats that can be transformed i…☆40Updated 2 months ago
- ☆12Updated 6 years ago
- ☆18Updated 6 years ago
- A framework for FPGA emulation of mixed-signal systems☆34Updated 3 years ago
- Hardware and script files related to dynamic partial reconfiguration☆9Updated 6 years ago
- Supporting Vector Machine Classsfications Using High-Level Synthesis☆7Updated 6 years ago