Ashwin-op / CMOS_Circuit_GeneratorLinks
Converting Boolean expressions to CMOS Circuits
☆11Updated 4 years ago
Alternatives and similar repositories for CMOS_Circuit_Generator
Users that are interested in CMOS_Circuit_Generator are comparing it to the libraries listed below
Sorting:
- Convert C files into Verilog☆17Updated 6 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆15Updated 4 years ago
- A copy of the latest version of MVSIS☆11Updated 4 years ago
- Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !☆13Updated 6 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Updated last month
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Updated 4 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 10 months ago
- Analog Circuit Simulator☆21Updated 10 months ago
- 32-bit RISC-V microcontroller☆10Updated 3 years ago
- Power grid analysis☆19Updated 4 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆36Updated last year
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆16Updated last year
- Annealing-based PCB placement tool☆39Updated 5 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 3 years ago
- ☆16Updated 5 years ago
- ☆31Updated 4 years ago
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆34Updated 2 years ago
- Gate-Level Simulation on a GPU☆10Updated 8 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆12Updated 11 years ago
- This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.☆14Updated 7 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆12Updated 5 years ago
- ☆25Updated 4 years ago
- A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …☆31Updated 10 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Supporting Vector Machine Classsfications Using High-Level Synthesis☆7Updated 7 years ago
- C++ Library for Quantum State Preparation (QSP)☆12Updated 2 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆34Updated last month
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 11 years ago