Alternatives and similar repositories for ece5960

Users that are interested in ece5960 are comparing it to the libraries listed below

• tsung-wei-huang / cs1410-40
  Object-Oriented Programming
  ☆12Updated 3 years ago
• tsung-wei-huang / ece6960-heterogeneous-programming
  Heterogeneous Programming
  ☆17Updated 2 years ago
• ckchengucsd / ILP-SAT-Detailed-Router
  ILP SAT Detailed Router
  ☆11Updated 5 years ago
• NVlabs / iccad2020-GPUgatesim
  ☆13Updated 4 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆25Updated 2 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• daitoto / EDA-wiki
  EDA wiki
  ☆54Updated 2 years ago
• kumasento / polsca
  Polyhedral High-Level Synthesis in MLIR
  ☆30Updated 2 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆108Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated this week
• Junyi-Liu / benchmarks-HLS
  Benchmarks, testbenches, and transformed codes for high-level synthesis research
  ☆13Updated 7 years ago
• natu4u / GSOC_TensorCore
  TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
  ☆21Updated 3 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆36Updated 10 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• esa-tu-darmstadt / spn-compiler
  Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.
  ☆23Updated 5 months ago
• ucb-bar / riscv-blas
  Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
  ☆19Updated 5 years ago
• aolofsson / IDEA
  ☆33Updated 5 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• ucb-ee290c / fa18-smartnic
  SmartNIC
  ☆14Updated 6 years ago
• UCLA-VAST / soda
  Stencil with Optimized Dataflow Architecture
  ☆15Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• spcl / FBLAS
  BLAS implementation for Intel FPGA
  ☆78Updated 4 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• Blaok / tapa
  TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…
  ☆19Updated 8 months ago
• antmicro / verilator-old-archived
  ☆22Updated 2 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 9 months ago