Alternatives and similar repositories for My-RISCV64-CORE-writing

Users that are interested in My-RISCV64-CORE-writing are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆86Updated last month
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆113Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆152Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆60Updated 3 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆146Updated 2 years ago
• leesum1 / ysyx
  一生一芯项目
  ☆13Updated last year
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆38Updated 4 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆118Updated last month
• RV-BOSC / OpenNoC
  ☆163Updated last month
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆157Updated last week
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆48Updated 10 months ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 10 months ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆24Updated last year
• ForrestBlue / cortexm0ds
  ☆65Updated 9 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆75Updated 3 years ago
• yyNoBug / RISCV-CPU
  A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…
  ☆9Updated 5 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• Jasonyanyusong / ysyx-npc-workbench
  一生一芯RISCV处理器核代码仓库（包括相关工具）
  ☆14Updated 9 months ago