leesum1 / ysyxView external linksLinks
一生一芯项目
☆18Oct 28, 2023Updated 2 years ago
Alternatives and similar repositories for ysyx
Users that are interested in ysyx are comparing it to the libraries listed below
Sorting:
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆22Jan 13, 2025Updated last year
- 一生一芯RISCV处理器核代码仓库（包括相关工具）☆15Sep 11, 2024Updated last year
- 一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆34Jul 17, 2022Updated 3 years ago
- ☆72Apr 23, 2023Updated 2 years ago
- ☆12May 8, 2025Updated 9 months ago
- 抄nemu的同学点个star好嘛☆155Jul 20, 2016Updated 9 years ago
- 2020秋-南大数电实验☆10Jan 24, 2021Updated 5 years ago
- 中国科学技术大学龙芯杯参赛作品仓库合集☆16Oct 2, 2024Updated last year
- ☆70Aug 30, 2022Updated 3 years ago
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- TDL-SDK samples for SDK V1 Duo(CV180X)☆14Feb 6, 2024Updated 2 years ago
- This is an IDE for YSYX_NPC debuging☆12Dec 10, 2024Updated last year
- Complete NEMU based on RISC-V instruction set☆15Apr 10, 2024Updated last year
- A Zero Cost Abstruction of FSM(Finite State Machine) circuits based on chisel3.☆13Oct 8, 2021Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- A usb FPGA board based Logic analyzer （逻辑分析仪）☆17Nov 14, 2022Updated 3 years ago
- This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…☆17Sep 29, 2024Updated last year
- Sample project with ssd1306 and MAX30102☆14Dec 29, 2022Updated 3 years ago
- 本工程用FPGA和python实现一个简单的8路输入逻辑分析仪☆19Aug 20, 2017Updated 8 years ago
- Gigabit Ethernet UDP communication driver☆80Jul 26, 2019Updated 6 years ago
- 我的一生一芯项目☆16Dec 14, 2021Updated 4 years ago
- ☆21Apr 8, 2025Updated 10 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22May 7, 2024Updated last year
- Basic chisel difftest environment for RTL design (WIP☆20Mar 8, 2025Updated 11 months ago
- ☆20Mar 18, 2022Updated 3 years ago
- PositNN - Framework for training and inference with neural nets usings posits☆20Jan 22, 2022Updated 4 years ago
- ☆90Nov 12, 2025Updated 3 months ago
- ☆22Nov 25, 2023Updated 2 years ago
- RISC-V SIMD Superscalar Dual-Issue Processor☆27Apr 24, 2025Updated 9 months ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆24Oct 1, 2022Updated 3 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆29Nov 30, 2022Updated 3 years ago
- Posit Arithmetic Cores generated with FloPoCo☆28Jun 25, 2024Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Feb 25, 2025Updated 11 months ago
- riscv32i-cpu☆18Nov 20, 2020Updated 5 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 4 months ago
- How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design☆625Aug 13, 2024Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 3 weeks ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- ☆28Oct 3, 2022Updated 3 years ago