Alternatives and similar repositories for PipelineCPU

Users that are interested in PipelineCPU are comparing it to the libraries listed below

• SakuraILU / NJU-ICS2021-PA
  NJU ICS课程的PA实验，非常棒的一个大项目，受益匪浅！一栈式打通虚拟机NEMU、操作系统NLiteOS和应用层
  ☆49Updated 3 years ago
• TCL606 / MipsPipeline
  Mips五级流水线CPU
  ☆44Updated 2 years ago
• Gugugugugutian / WHU-CPU-RISC-V
  武汉大学计算机组成与设计课程单周期CPU处理器实现，使用RISC-V语言实现。
  ☆10Updated last year
• MaZirui2001 / USTC-NSCSCC
  中国科学技术大学龙芯杯参赛作品仓库合集
  ☆15Updated last year
• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆88Updated 9 months ago
• y0fy / CO-lab-material-CQU
  重庆大学计算机组成原理、硬件综合设计实验材料
  ☆37Updated 4 years ago
• preminstrel / awesome-seu
  Awesome SEU
  ☆38Updated 2 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆92Updated 3 years ago
• xiazhuo / nscc2022_personal
  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
  ☆75Updated last year
• panxuc / xucpu
  NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖
  ☆10Updated last year
• yusanshi / Greedy-Snake-Verilog
  Greedy Snake game on Nexys 4 DDR with Verilog.
  ☆29Updated 3 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆61Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆143Updated last year
• LC044 / CPU
  五级流水线CPU设计
  ☆13Updated 2 years ago
• Timothy-Liuxf / PipelineCPU
  清华大学电子工程系数字逻辑与处理器基础实验大作业——流水线 CPU
  ☆12Updated 4 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆29Updated 4 years ago
• jhdjames37 / RISC-V-CPU-simple
  清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期，造台计算机」
  ☆20Updated 2 years ago
• TheRainstorm / PiplineMIPS
  A 5-level pipelined MIPS CPU with branch prediction and great cache.
  ☆20Updated 4 years ago
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆53Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆48Updated 3 years ago
• npu-cs / SurviveNWPU-CSManual
  A Manual on Surviving in CS of NWPU
  ☆54Updated 2 years ago
• Kristoff-starling / ProjectN-CPU
  Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
  ☆14Updated 3 years ago
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆30Updated 9 months ago
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆15Updated last year
• cebarobot / UCAS-Computer-Architecture-Lab
  计算机体系结构研讨课 2020秋季 UCAS 《CPU设计实战》 工程环境及 RTL 代码合集
  ☆18Updated 4 years ago
• yueyang2000 / riscv-cpu
  RISC-V multi cycle CPU. Project of Computer Organization (THU 2020)
  ☆17Updated 2 years ago
• Sevenqi7 / NSCSCC-2022
  2022龙芯杯个人赛三等奖作品
  ☆14Updated 2 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• IA-C-Lab-Fudan / KWS-SoC
  This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.
  ☆53Updated 5 years ago
• Xinyang-ZHANG / RISC_V_RV32I_5stage_pipeline
  5 stage pipeline, single cycle risc-V implementation
  ☆24Updated last year