Alternatives and similar repositories for UCAS-Advanced-Computer-Architecture-OpenROAD-flow:

Users that are interested in UCAS-Advanced-Computer-Architecture-OpenROAD-flow are comparing it to the libraries listed below

• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆23Updated 2 years ago
• THU-DSP-LAB / ventus-gpgpu-isa-simulator
  Ventus GPGPU ISA Simulator Based on Spike
  ☆42Updated last month
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆24Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 9 months ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆10Updated 4 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated last month
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆70Updated 3 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆62Updated 8 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆29Updated 3 months ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆73Updated last week
• CherrySprings / CherrySprings
  ☆17Updated last year
• OSCPU / yosys-sta
  ☆58Updated 2 months ago
• sharc-lab / FPGA_ECE8893
  ☆33Updated this week
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆59Updated 2 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆48Updated 3 months ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• lizhirui / DreamCoreV2
  ☆22Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆87Updated 5 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆61Updated last year
• OSCPU / ysyxSoC
  ☆79Updated last month
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆51Updated 4 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated last year
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆23Updated 7 months ago
• hngenc / stellar
  ☆24Updated 4 months ago
• compiler-dev / llvm-rv
  Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension
  ☆43Updated 4 years ago