中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
☆30May 30, 2020Updated 6 years ago
Alternatives and similar repositories for UCAS-Advanced-Computer-Architecture-OpenROAD-flow
Users that are interested in UCAS-Advanced-Computer-Architecture-OpenROAD-flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 国科大部分课程期末复习资料☆18Oct 31, 2022Updated 3 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆14Dec 4, 2025Updated 7 months ago
- 中国科学院大学（国科大）研一课程☆19May 24, 2023Updated 3 years ago
- UCAS-2022秋季学期计算机算法设计与分析(刘玉贵老师)课程资料总结☆24Dec 29, 2022Updated 3 years ago
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- 国科大计算机相关课程资料(2021-2022学年)☆37Jun 12, 2022Updated 4 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 6 years ago
- 存放在UCAS学习时的课程相关资料☆22Jul 8, 2023Updated 3 years ago
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆14Sep 22, 2025Updated 10 months ago
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- UCAS 高性能计算系统 mpi☆12Jun 14, 2019Updated 7 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 5 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 国科大高等数字集成电路分析与设计课程2022fall☆31Dec 13, 2022Updated 3 years ago
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13May 31, 2024Updated 2 years ago
- Some common CUDA kernel implementations (Not the fastest).☆30Jun 24, 2026Updated last month
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆19Aug 27, 2025Updated 10 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆19Apr 17, 2021Updated 5 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Oct 25, 2024Updated last year
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 3 years ago
- 哈尔滨工业大学（深圳）2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 3 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- 21-22春 智能计算系统实验 中国科学院大学☆31May 5, 2022Updated 4 years ago
- Archive of the git branches attached to tickets on https://trac.sagemath.org/ before the migration to GitHub (Jan 30, 2023)☆11Jan 30, 2023Updated 3 years ago
- Model LLM inference on single-core dataflow accelerators☆19Dec 16, 2025Updated 7 months ago
- The specification of the LDBC Financial Benchmark☆19Jan 9, 2026Updated 6 months ago
- ☆16Jul 14, 2024Updated 2 years ago
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- ☆12Sep 18, 2024Updated last year
- A graph pattern mining framework for large graphs on gpu.☆16Dec 9, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Train a neural network to produce latex source code which generates a given pdf file☆13May 3, 2017Updated 9 years ago
- Three-phase inverter operating at AC100V.☆20Oct 8, 2023Updated 2 years ago
- UCAS High Performance Computing System 国科大高性能计算系统复习及试题☆17May 27, 2022Updated 4 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- ☆39Updated this week
- ☆32Aug 24, 2022Updated 3 years ago
- This is a set of python codes that forecast electricity price in wholesale power markets using an integrated long-term recurrent convolut…☆16Oct 14, 2022Updated 3 years ago