中国科学院大学高级计算机体系结构课程作业:使用OpenROAD-flow完成RTL到GDS全流程
☆30May 30, 2020Updated 5 years ago
Alternatives and similar repositories for UCAS-Advanced-Computer-Architecture-OpenROAD-flow
Users that are interested in UCAS-Advanced-Computer-Architecture-OpenROAD-flow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 国科大部分课程期末复习资料☆18Oct 31, 2022Updated 3 years ago
- 5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany☆13Dec 4, 2025Updated 3 months ago
- 存放在UCAS学习时的课程相关资料☆22Jul 8, 2023Updated 2 years ago
- 中国科学院大学(国科大)研一课程☆18May 24, 2023Updated 2 years ago
- UCAS-2022秋季学期计算机算法设计与分析(刘玉贵老师)课程资料总结☆25Dec 29, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Language for simplifying parameterized RTL design☆13Nov 6, 2024Updated last year
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Sep 22, 2025Updated 6 months ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- Implement BinaryNet of CNN with chainer☆11May 5, 2016Updated 9 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 3 years ago
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆11Feb 23, 2023Updated 3 years ago
- Some common CUDA kernel implementations (Not the fastest).☆29Dec 5, 2025Updated 3 months ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A graph pattern mining framework for large graphs on gpu.☆15Dec 9, 2024Updated last year
- 中国科学院大学2022秋季学期智能计算系统实验-陈云霁☆11Jan 3, 2023Updated 3 years ago
- 【2024年新版】国科大 陈云霁 智能计算系统AICS实验代码☆13May 31, 2024Updated last year
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 6 months ago
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 3 years ago
- The specification of the LDBC Financial Benchmark☆19Jan 9, 2026Updated 2 months ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆19Apr 17, 2021Updated 4 years ago
- A benchmark suite for Graph Machine Learning☆19Oct 8, 2024Updated last year
- 国科大高等数字集成电 路分析与设计课程2022fall☆31Dec 13, 2022Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Oct 25, 2024Updated last year
- Archive of the git branches attached to tickets on https://trac.sagemath.org/ before the migration to GitHub (Jan 30, 2023)☆11Jan 30, 2023Updated 3 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆12Apr 18, 2024Updated last year
- Arya: Arbitrary Graph Pattern Mining with Decomposition-based Sampling☆16Sep 27, 2023Updated 2 years ago
- 国科大深度学习课程资料 2022年春季课程 王亮、黄岩教师授课☆13Jun 1, 2022Updated 3 years ago
- ☆15Jul 14, 2024Updated last year
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 5 years ago
- ☆12Sep 18, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Some "Formula Translations" for Yousef Saad's book "Iterative Methods for Sparse Linear Systems (2nd Edition)"☆13Jan 14, 2018Updated 8 years ago
- Train a neural network to produce latex source code which generates a given pdf file☆13May 3, 2017Updated 8 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- GPGPU-Sim 中文注释版代码,包含 GPGPU-Sim 模拟器的最新版代码,经过中文注释,以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- ☆32Aug 24, 2022Updated 3 years ago
- This is a set of python codes that forecast electricity price in wholesale power markets using an integrated long-term recurrent convolut…☆15Oct 14, 2022Updated 3 years ago