AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
☆19Updated 3 months ago
Alternatives and similar repositories for 2D-Binary-Content-Addressable-Memory-BCAM:
Users that are interested in 2D-Binary-Content-Addressable-Memory-BCAM are comparing it to the libraries listed below
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 weeks ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆37Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 9 months ago
- ☆24Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- Verilog RTL Design☆31Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated 2 months ago
- ☆26Updated last year
- Verilog Content Addressable Memory Module☆101Updated 2 years ago
- ☆20Updated 5 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆33Updated 10 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 6 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Generate UVM testbench framework template files with Python 3☆25Updated 5 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- ☆18Updated 4 years ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago