AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAMLinks
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
☆20Updated 6 months ago
Alternatives and similar repositories for 2D-Binary-Content-Addressable-Memory-BCAM
Users that are interested in 2D-Binary-Content-Addressable-Memory-BCAM are comparing it to the libraries listed below
Sorting:
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆60Updated 4 years ago
- Python Tool for UVM Testbench Generation☆52Updated last year
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- SoC Based on ARM Cortex-M3☆32Updated 2 weeks ago
- ☆25Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆20Updated 5 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆34Updated 10 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Ethernet interface modules for Cocotb☆65Updated last year
- Systemverilog DPI-C call Python function☆23Updated 4 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated last year
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago