AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
☆18Updated 9 years ago
Related projects ⓘ
Alternatives and complementary repositories for 2D-Binary-Content-Addressable-Memory-BCAM
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- General Purpose AXI Direct Memory Access☆44Updated 5 months ago
- Python Tool for UVM Testbench Generation☆49Updated 5 months ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago
- SoC Based on ARM Cortex-M3☆25Updated 5 months ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆40Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆14Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 6 months ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- Repository gathering basic modules for CDC purpose☆50Updated 4 years ago
- YosysHQ SVA AXI Properties☆31Updated last year
- PCI Express controller model☆44Updated 2 years ago
- ☆20Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆41Updated 7 months ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- Synopsys Design compiler, VCS and Tetra-MAX☆15Updated 6 years ago
- ☆39Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- ☆22Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- ☆26Updated last year