A full-speed device-side USB peripheral core written in Verilog.
☆244Oct 30, 2022Updated 4 years ago
Alternatives and similar repositories for usbcorev
Users that are interested in usbcorev are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Basic USB-CDC device core (Verilog)☆95May 15, 2021Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆103Jun 6, 2020Updated 6 years ago
- Nitro USB FPGA core☆91Mar 1, 2026Updated 8 months ago
- USB3 SuperSpeed (5Gbps) and SuperSpeedPlus (10Gbps) for FPGAs without external chip: PHY + Device Core in LiteX.☆274Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Various HDL (Verilog) IP Cores☆939Jul 1, 2021Updated 5 years ago
- USB 1.1 PHY☆12Jul 17, 2014Updated 12 years ago
- An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA comm…☆934Dec 6, 2024Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 8 years ago
- USB 2.0 Device IP Core☆76Oct 1, 2017Updated 9 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆41Dec 2, 2018Updated 7 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆194Mar 10, 2024Updated 2 years ago
- USB Serial on the TinyFPGA BX☆146Jun 20, 2021Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆34Nov 23, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- An open source USB bootloader for FPGAs☆403Sep 15, 2023Updated 3 years ago
- Send video/audio over HDMI on an FPGA☆1,308Jul 13, 2026Updated 3 months ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- FPGA USB stack written in LiteX☆138Jun 5, 2022Updated 4 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆87Sep 7, 2020Updated 6 years ago
- High Speed USB 2.0 capture device based on miniSpartan6+☆60May 26, 2020Updated 6 years ago
- SuperSpeed USB 3.0 FPGA platform☆274Apr 9, 2015Updated 11 years ago
- USB Full Speed PHY☆49May 3, 2020Updated 6 years ago
- Verilog SDRAM memory controller☆388May 13, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SPIREG - SPI slave logic for register access☆11Nov 12, 2025Updated 11 months ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆276Mar 15, 2019Updated 7 years ago
- RISC-V GPGPU☆40Mar 6, 2020Updated 6 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆644Oct 10, 2021Updated 5 years ago
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆259Nov 29, 2018Updated 7 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆112Oct 3, 2019Updated 7 years ago
- Verilog Ethernet components for FPGA implementation☆3,143Feb 27, 2025Updated last year
- USB2.0 Device Controller IP Core☆21Aug 18, 2023Updated 3 years ago
- Audio controller (I2S, SPDIF, DAC)☆101Sep 1, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Using the TinyFPGA BX USB code in user designs☆53Jan 31, 2019Updated 7 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Verilog PCI express components☆1,676Apr 26, 2024Updated 2 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆13Aug 8, 2017Updated 9 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- USB2.0 Verilog☆20Apr 21, 2019Updated 7 years ago