avakar / usbcorevLinks
A full-speed device-side USB peripheral core written in Verilog.
☆235Updated 3 years ago
Alternatives and similar repositories for usbcorev
Users that are interested in usbcorev are comparing it to the libraries listed below
Sorting:
- USB3 PIPE interface for Xilinx 7-Series☆234Updated 3 years ago
- WISHBONE SD Card Controller IP Core☆128Updated 3 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆328Updated 3 weeks ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆260Updated 6 years ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆242Updated 5 years ago
- Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…☆258Updated 3 months ago
- A simple, basic, formally verified UART controller☆312Updated last year
- Basic USB-CDC device core (Verilog)☆79Updated 4 years ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆286Updated last year
- FPGA Logic Analyzer and GUI☆143Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆91Updated 3 years ago
- SPI Slave for FPGA in Verilog and VHDL☆214Updated last year
- Verilog UART☆186Updated 12 years ago
- SPI Master for FPGA - VHDL and Verilog☆305Updated 2 years ago
- Opensource DDR3 Controller☆390Updated 5 months ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆175Updated last year
- 720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)☆285Updated 4 years ago
- SPI master and SPI slave for FPGA written in VHDL☆180Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- Verilog SDRAM memory controller☆348Updated 8 years ago
- Small footprint and configurable DRAM core☆450Updated 3 weeks ago
- Verilog digital signal processing components☆159Updated 3 years ago
- Verilog wishbone components☆121Updated last year
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆183Updated last year
- ☆87Updated 8 years ago
- Verilog SPI master and slave☆60Updated 9 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 8 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆528Updated 4 years ago
- Verilog implementation of a RISC-V core☆128Updated 7 years ago