Alternatives and similar repositories for usbcorev:

Users that are interested in usbcorev are comparing it to the libraries listed below

• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆212Updated 3 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆277Updated last week
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆122Updated 2 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆299Updated last year
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆247Updated 6 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆319Updated 2 weeks ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆199Updated 11 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆443Updated 3 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆77Updated 3 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆228Updated 5 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆265Updated last year
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆125Updated 2 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆410Updated last week
• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆282Updated last year
• jamieiles / uart
  Verilog UART
  ☆163Updated 11 years ago
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆277Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆66Updated 7 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆327Updated 7 years ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆241Updated 11 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆551Updated 3 weeks ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆330Updated last year
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆382Updated this week
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆779Updated 3 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 4 years ago
• cliffordwolf / SimpleVOut
  A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
  ☆237Updated 6 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆146Updated 2 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆157Updated last month
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆80Updated 2 years ago