Audio controller (I2S, SPDIF, DAC)
☆95Sep 1, 2019Updated 6 years ago
Alternatives and similar repositories for core_audio
Users that are interested in core_audio are comparing it to the libraries listed below
Sorting:
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 5 years ago
- fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard☆16Aug 3, 2019Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆74Jun 16, 2022Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- ☆27Apr 13, 2022Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆83Aug 9, 2020Updated 5 years ago
- i2s core, with support for both transmit and receive☆32May 24, 2018Updated 7 years ago
- Open Source Windows UAC2 driver☆20Feb 24, 2013Updated 13 years ago
- A high-performance DIY audio DAC☆20Aug 16, 2020Updated 5 years ago
- I2S transciever implemented in Verilog HDL☆32Oct 11, 2017Updated 8 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- STM32 USB Device Audio Streaming software expansion for STM32Cube, for mockups☆22May 12, 2019Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆18Mar 4, 2019Updated 7 years ago
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆34May 28, 2021Updated 4 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆27Sep 2, 2019Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- USB serial device (CDC-ACM)☆45Jun 28, 2020Updated 5 years ago
- Basic USB-CDC device core (Verilog)☆88May 15, 2021Updated 4 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- ULPI Link Wrapper (USB Phy Interface)☆36May 3, 2020Updated 5 years ago
- FIR implemention with Verilog☆50May 18, 2019Updated 6 years ago
- Cheapest UAC2 using STM32F407+USB3300☆21Feb 26, 2025Updated last year
- Programmable multichannel ADPCM decoder for FPGA☆25Dec 28, 2020Updated 5 years ago
- I2S to S/PDIF conversion on SiPeed Tang Nano (GOWIN GW1N-LV1) which aims to convert Nintendo Switch's internal I2S signal.☆38Aug 15, 2020Updated 5 years ago
- LMS-Adaptive Filter implement using verilog and Matlab☆48Oct 21, 2016Updated 9 years ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 13 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- USB audio interface,design by STM32 and EP4CE6 FPGA,support DSD☆15Jan 20, 2017Updated 9 years ago
- verilog example to drive PCM5102 DAC with FPGA☆18Apr 30, 2018Updated 7 years ago
- Open Hardware Zynq System on Module☆31Jul 25, 2015Updated 10 years ago
- ☆20Jun 18, 2022Updated 3 years ago
- 这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西☆36Nov 11, 2017Updated 8 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆268Mar 15, 2019Updated 7 years ago