ultraembedded / core_audioLinks
Audio controller (I2S, SPDIF, DAC)
☆88Updated 5 years ago
Alternatives and similar repositories for core_audio
Users that are interested in core_audio are comparing it to the libraries listed below
Sorting:
- Basic USB-CDC device core (Verilog)☆81Updated 4 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆72Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆72Updated 3 years ago
- USB 2.0 Device IP Core☆68Updated 7 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Updated 3 years ago
- USB serial device (CDC-ACM)☆40Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆92Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- MIPI DSI controller☆79Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆43Updated 3 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆117Updated 4 years ago
- Source code of MIPI DSI Bridge Published on https://www.circuitvalley.com☆109Updated last year
- Delta Sigma DAC FPGA☆43Updated 6 months ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆77Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆29Updated 5 years ago
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆77Updated 5 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- Verilog modules required to get the OV7670 camera working☆73Updated 7 years ago
- I2S transciever implemented in Verilog HDL☆31Updated 7 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆62Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 7 months ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆44Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆95Updated 5 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago