C-L-G / My_Opensource_AZPR_SOCLinks
根据最近看的一本书编写的对应RTL以及Testbench
☆20Updated 8 years ago
Alternatives and similar repositories for My_Opensource_AZPR_SOC
Users that are interested in My_Opensource_AZPR_SOC are comparing it to the libraries listed below
Sorting:
- 用Altera FPGA芯片自制CPU☆42Updated 11 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆21Updated 2 years ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Updated 7 years ago
- ☆16Updated 6 years ago
- Verification of Ethernet Switch System Verilog☆11Updated 9 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- USB 2.0 Device IP Core☆71Updated 8 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆18Updated 6 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13Updated 6 years ago
- Testbenches for HDL projects☆21Updated last week
- ☆31Updated 4 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 8 years ago
- 标准视频时序生成器☆10Updated 5 years ago
- minimal code to access ps DDR from PL☆21Updated 6 years ago
- Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3☆37Updated 12 years ago
- Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation☆12Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆75Updated last year
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- 8051 core☆109Updated 11 years ago
- A Voila-Jones face detector hardware implementation☆33Updated 6 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 7 years ago
- QSPI for SoC☆23Updated 5 years ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆20Updated 8 months ago
- FPGA Technology Exchange Group相关文件管理☆53Updated last week