Alternatives and similar repositories for My_Opensource_AZPR_SOC

Users that are interested in My_Opensource_AZPR_SOC are comparing it to the libraries listed below

• zhangly / azpr_cpu
  用Altera FPGA芯片自制CPU
  ☆41Updated 11 years ago
• redchenjs / wujian100_open
  平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
  ☆19Updated last year
• yedk / arm_cortex_m0_xillinx
  基于arm cortex-m0内核的xillinx fpga sopc工程项目
  ☆13Updated 6 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• wuhanstudio / picorv32_tang
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆28Updated last year
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆20Updated 5 years ago
• lulinchen / face_detect_open
  A Voila-Jones face detector hardware implementation
  ☆32Updated 6 years ago
• freecores / 8051
  8051 core
  ☆106Updated 11 years ago
• antmicro / openssd-nvme
  ☆29Updated 4 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆41Updated 3 years ago
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆18Updated 5 years ago
• briandong / regModel
  This script builds the UVM register model, based on pre-defined address map in markdown (mk) style
  ☆12Updated 7 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• Elrori / OV_camera_on_FPGA
  OV7670 (Verilog HDL)Drive for FPGA
  ☆17Updated 6 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 8 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆47Updated last week
• rakeshgehalot / Ethernet_switch_verification
  Verification of Ethernet Switch System Verilog
  ☆11Updated 8 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆19Updated this week
• sunzhengyuan / auto_simulate
  Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation
  ☆12Updated 6 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• dineshannayya / usb1_host
  USB1.1 Host Controller + PHY
  ☆14Updated 4 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆38Updated 3 years ago
• For-up / SEA-S7Guess
  SEA-S7_gesture recognition
  ☆16Updated 5 years ago
• verimake-team / SparkRoad-V
  ☆64Updated 6 months ago
• Tian-Changsong / Verilog-Automatic
  Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
  ☆37Updated 12 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆85Updated 5 years ago