makestuff / altera-pcie
Simple framework for building PCIe-based solutions for Altera FPGAs
☆42Updated 4 years ago
Related projects: ⓘ
- A wishbone controlled scope for FPGA's☆72Updated 8 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆57Updated 3 weeks ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆82Updated 4 years ago
- Small footprint and configurable SPI core☆38Updated this week
- Small footprint and configurable Inter-Chip communication cores☆53Updated this week
- FPGA USB 1.1 Low-Speed Implementation☆32Updated 5 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆42Updated 8 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆33Updated 8 months ago
- FPGA board-level debugging and reverse-engineering tool☆28Updated last year
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆49Updated last year
- SoftCPU/SoC engine-V☆54Updated last year
- Extensible FPGA control platform☆52Updated last year
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago
- Generic Logic Interfacing Project☆44Updated 4 years ago
- CMod-S6 SoC☆35Updated 6 years ago
- Small footprint and configurable SATA core☆123Updated 3 months ago
- FPGA reference design for the the Swerv EH1 Core☆65Updated 4 years ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆13Updated 3 years ago
- Wishbone controlled I2C controllers☆40Updated 6 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆39Updated 5 months ago
- Small footprint and configurable JESD204B core☆39Updated 3 months ago
- Sample minimal Vivado project for Parallella FPGA☆42Updated 8 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆27Updated 7 years ago
- Triple Modular Redundancy☆23Updated 5 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆51Updated last year
- SymbiFlow WIP changes for Yosys Open SYnthesis Suite☆37Updated 6 months ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆36Updated 4 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- ☆44Updated 2 years ago