SiLab-Bonn / basil
A data acquisition framework in Python and Verilog.
☆41Updated last week
Alternatives and similar repositories for basil:
Users that are interested in basil are comparing it to the libraries listed below
- Extensible FPGA control platform☆57Updated last year
- An abstract language model of VHDL written in Python.☆50Updated this week
- ☆26Updated last year
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- Framework Open EDA Gui☆63Updated 2 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- Audio filtering with pyfda and cocotb☆10Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆52Updated last week
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- Open Source Verification Bundle for VHDL and System Verilog☆43Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆65Updated 2 weeks ago
- This repository contains synthesizable examples which use the PoC-Library.☆36Updated 4 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- A getting started presentation (with examples) about how to use FLOSS for FPGA development.☆35Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆52Updated last week
- An example Python-based MDV testbench for apbi2c core☆30Updated 6 months ago
- An open-source HDL register code generator fast enough to run in real time.☆54Updated this week
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆54Updated this week
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated 2 weeks ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Virtual development board for HDL design☆40Updated last year
- Library of reusable VHDL components☆27Updated 11 months ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 7 months ago
- ☆53Updated last year
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆31Updated 5 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year