jobisoft / jTDCLinks
FPGA based 30ps RMS TDCs
☆91Updated 7 years ago
Alternatives and similar repositories for jTDC
Users that are interested in jTDC are comparing it to the libraries listed below
Sorting:
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆68Updated 10 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆70Updated 4 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆61Updated 3 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆58Updated 4 years ago
- Verilog implementation of a tapped delay line TDC☆46Updated 7 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- Project: Precise Measure of time delays in FPGA☆30Updated 8 years ago
- Time to Digital Converter on an FPGA☆18Updated 5 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆76Updated 2 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆61Updated 11 months ago
- Capture images/video from a Raspberry Pi Camera (MIPI CSI-2) with an FPGA☆73Updated 5 years ago
- A Time to Digital Converter (TDC) on a Xilinx Virtex 5 FPGA.☆23Updated 8 years ago
- SEA-S7_gesture recognition☆17Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Basic USB-CDC device core (Verilog)☆85Updated 4 years ago
- USB 2.0 Device IP Core☆74Updated 8 years ago
- 【例程】国产高云FPGA 开发板及其工程☆43Updated last year
- FPGA Technology Exchange Group相关文件管理☆67Updated 3 weeks ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Updated 10 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆45Updated 4 years ago
- This is xc7z020clg400 FPGA hardware core board design☆72Updated 2 years ago
- Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.☆32Updated 5 years ago
- AD7606 driver verilog☆45Updated 6 years ago
- Repository for the development of an FPGA based DSP Lock-In Amplifier☆71Updated 2 years ago
- A Time to Digital Converter designed for Xilinx 7-Series FPGAs☆35Updated 5 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated 2 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆127Updated 4 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆83Updated 4 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago