nickmqb / wyreLinks
Hardware definition language that compiles to Verilog
☆106Updated 4 years ago
Alternatives and similar repositories for wyre
Users that are interested in wyre are comparing it to the libraries listed below
Sorting:
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆86Updated 5 years ago
- A bit-serial CPU written in VHDL, with a simulator written in C.☆130Updated last year
- Playground for VGA projects on Tiny Tapeout☆65Updated 2 weeks ago
- ☆96Updated 4 years ago
- Documenting Lattice's 28nm FPGA parts☆145Updated last year
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆223Updated last year
- 👇 Add capacitive touch buttons to any FPGA!☆102Updated 3 years ago
- WIP 100BASE-TX PHY☆76Updated 10 months ago
- A C++ to Verilog translation tool with some basic guarantees that your code will work.☆173Updated 7 months ago
- A voxel game/Minecraft clone for the iCE40 UP5K FPGA☆210Updated 4 years ago
- UPduino 3.0: new 4 layer layout, various other improvements☆343Updated 8 months ago
- The Zylin ZPU☆244Updated 10 years ago
- A Forth CPU and System on a Chip, based on the J1, written in VHDL☆361Updated last year
- A configurable RTL to bitstream FPGA toolchain☆44Updated this week
- CHIP-8 console on FPGA☆199Updated 6 years ago
- An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one☆53Updated 4 months ago
- Compact FPGA game console☆166Updated last year
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆44Updated last year
- A computer for human beings.☆45Updated 11 months ago
- Unofficial Yosys WebAssembly packages☆72Updated last week
- The J1 CPU☆171Updated 4 years ago
- Hot Reconfiguration Technology demo☆40Updated 3 years ago
- A collection of tools for developing for Fomu☆84Updated 2 years ago
- ☆41Updated 4 years ago
- i8080 precise replica in Verilog, based on reverse engineering of real die☆159Updated 6 years ago
- Graphics demos☆111Updated last year
- MRSIC32 ISA documentation and development☆91Updated 2 years ago
- An attempt to recreate the RP2040 PIO in an FPGA☆303Updated last year
- A collection of common Bluespec interfaces/modules.☆102Updated last year
- Experiments with Yosys cxxrtl backend☆50Updated 8 months ago