ChenJianyunp / FPGA-Snappy-DecompressorLinks
A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.
☆24Updated 2 years ago
Alternatives and similar repositories for FPGA-Snappy-Decompressor
Users that are interested in FPGA-Snappy-Decompressor are comparing it to the libraries listed below
Sorting:
- ☆69Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆25Updated 3 years ago
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- Virtio implementation in SystemVerilog☆48Updated 7 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated last week
- ☆81Updated last year
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆26Updated 4 years ago
- Ethernet switch implementation written in Verilog☆54Updated 2 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 10 years ago
- PCI Express controller model☆70Updated 3 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 3 months ago
- ☆28Updated last year
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆52Updated 4 months ago
- BlackParrot on Zynq☆47Updated 2 weeks ago
- Distributed Accelerator OS☆63Updated 3 years ago
- Simple hash table on Verilog (SystemVerilog)☆50Updated 9 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆127Updated 2 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 11 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆51Updated 4 years ago
- AMD OpenNIC driver includes the Linux kernel driver☆70Updated 11 months ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago