Xilinx / DSP-PYNQ
A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
☆37Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for DSP-PYNQ
- PYNQ Composabe Overlays☆67Updated 4 months ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆56Updated 4 years ago
- ☆18Updated 3 years ago
- Vitis Model Composer Examples and Tutorials☆73Updated this week
- Board repo for the ZCU216 RFSOC☆25Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆90Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 2 years ago
- Networking Overlay on PYNQ☆44Updated 5 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆30Updated 3 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- PYNQ support and examples for Kria SOMs☆91Updated 2 months ago
- Board files to build Ultra 96 PYNQ image☆151Updated 2 months ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆26Updated last year
- Python productivity for RFSoC platforms☆55Updated 5 months ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆79Updated last year
- RTL Verilog library for various DSP modules☆83Updated 2 years ago
- Verilog digital signal processing components☆104Updated 2 years ago
- Avnet Board Definition Files☆125Updated last week
- This store contains Configurable Example Designs.☆42Updated this week
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆102Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆30Updated last year
- ☆70Updated 11 months ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated this week
- ☆24Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆40Updated 2 years ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year