Alternatives and similar repositories for DSP-PYNQ

Users that are interested in DSP-PYNQ are comparing it to the libraries listed below

• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆62Updated 4 years ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆102Updated last week
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆103Updated 2 years ago
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 2 years ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆38Updated 3 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆76Updated this week
• strath-sdr / rfsoc_radio
  PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
  ☆37Updated 2 years ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆81Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• ATaylorCEngFIET / Vitis_Hero
  ☆28Updated 3 years ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, AUP UltraScale+ MPSoC academic board
  ☆26Updated 2 weeks ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆23Updated 3 years ago
• cathalmccabe / PYNQ_tutorials
  ☆92Updated last year
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆28Updated 2 years ago
• Xilinx / RFNoC-HLS-NeuralNet
  ☆107Updated 5 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆155Updated 6 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆222Updated last year
• Xilinx / RFSoC-MTS
  A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).
  ☆24Updated 2 years ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆67Updated 4 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆29Updated 3 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago