Alternatives and similar repositories for DSP-PYNQ:

Users that are interested in DSP-PYNQ are comparing it to the libraries listed below

• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆69Updated 7 months ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆80Updated this week
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆94Updated last year
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆25Updated 2 years ago
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆56Updated 4 years ago
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 2 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆27Updated 4 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆18Updated 3 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆81Updated last year
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆153Updated last month
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆47Updated 5 years ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆101Updated 4 months ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆96Updated 2 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆37Updated 5 years ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆32Updated 3 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆27Updated last year
• Xilinx / PYNQ-ZU
  PYNQ-ZU, XUP UltraScale+ MPSoC academic board
  ☆20Updated 4 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆129Updated last week
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• cathalmccabe / PYNQ_tutorials
  ☆73Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆49Updated last year
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆46Updated 2 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆61Updated 7 months ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆47Updated last year
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆58Updated last month
• ATaylorCEngFIET / Vitis_Hero
  ☆24Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆103Updated 6 years ago