Alternatives and similar repositories for DSP-PYNQ:

Users that are interested in DSP-PYNQ are comparing it to the libraries listed below

• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆71Updated 9 months ago
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆59Updated 4 years ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆26Updated 2 years ago
• MakarenaLabs / Common-PL-Devices-on-PYNQ
  Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
  ☆33Updated 3 years ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆100Updated last year
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆48Updated 6 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆49Updated 3 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 2 years ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆96Updated 2 weeks ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆101Updated 2 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, XUP UltraScale+ MPSoC academic board
  ☆23Updated last week
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 6 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆29Updated 4 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆30Updated 2 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆65Updated 10 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆55Updated 2 years ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆105Updated 7 months ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆154Updated 3 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆135Updated 2 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆48Updated last year
• sfox14 / pynq-ekf
  A multi-board Extended Kalman Filter (EKF)
  ☆31Updated 6 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆39Updated 2 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆38Updated 5 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆152Updated 3 years ago
• strath-sdr / rfsoc_frequency_planner
  An RFSoC Frequency Planner developed using Python.
  ☆25Updated last year
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆76Updated 9 months ago