dspsandbox / Pynq-Redpitaya-125Links
☆19Updated 7 months ago
Alternatives and similar repositories for Pynq-Redpitaya-125
Users that are interested in Pynq-Redpitaya-125 are comparing it to the libraries listed below
Sorting:
- ☆42Updated last week
- Repository for FPGA projects☆57Updated last month
- SDK for FPGA / Linux Instruments☆106Updated last week
- Collections of guides and projects related to testing RedPitaya☆56Updated 6 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆87Updated last year
- Python productivity for RFSoC platforms☆84Updated 2 weeks ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- Transform the Red Pitaya in an acquisition card☆35Updated 4 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Updated this week
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆67Updated 4 years ago
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆41Updated 3 years ago
- Serial communication link bit error rate tester simulator, written in Python.☆116Updated last week
- An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- Board repo for the ZCU216 RFSOC☆30Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- migen + misoc + redpitaya = digital servo☆41Updated 6 years ago
- A Python package to use FPGA development tools programmatically.☆142Updated 7 months ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆34Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK transceiver.☆108Updated 2 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya☆48Updated last month
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆122Updated 4 years ago
- Simple projects for the RedPitaya board that illustrate the use of standard IPs from Vivado in combination with modules written in Verilo…☆16Updated 3 months ago
- A collection of phase locked loop (PLL) related projects☆112Updated last year
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆238Updated 2 years ago
- Repository for the development of an FPGA based DSP Lock-In Amplifier☆72Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated 11 months ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago