hamsternz / Rudi-RV32I
A rudimental RISCV CPU supporting RV32I instructions, in VHDL
☆117Updated 4 years ago
Alternatives and similar repositories for Rudi-RV32I:
Users that are interested in Rudi-RV32I are comparing it to the libraries listed below
- Verilog implementation of a RISC-V core☆109Updated 6 years ago
- Verilog digital signal processing components☆129Updated 2 years ago
- An Open Source configuration of the Arty platform☆127Updated last year
- FuseSoC standard core library☆128Updated last month
- Yet Another RISC-V Implementation☆89Updated 5 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- SoC based on VexRiscv and ICE40 UP5K☆153Updated 11 months ago
- A utility for Composing FPGA designs from Peripherals☆171Updated 2 months ago
- ☆129Updated 3 months ago
- Basic RISC-V Test SoC☆116Updated 5 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 3 years ago
- Opensource DDR3 Controller☆279Updated this week
- Simple 8-bit UART realization on Verilog HDL.☆101Updated 10 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- WISHBONE SD Card Controller IP Core☆121Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆242Updated 6 years ago
- Basic RISC-V CPU implementation in VHDL.☆166Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆94Updated 3 years ago
- Announcements related to Verilator☆39Updated 4 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 4 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆75Updated last week
- ☆87Updated last year
- A simple implementation of a UART modem in Verilog.☆122Updated 3 years ago
- Verilog UART☆146Updated 11 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago