Alternatives and similar repositories for Rudi-RV32I:

Users that are interested in Rudi-RV32I are comparing it to the libraries listed below

• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆113Updated 6 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆119Updated 6 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆144Updated 9 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆132Updated last week
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆62Updated last month
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆176Updated 3 months ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆129Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated last week
• jamieiles / uart
  Verilog UART
  ☆153Updated 11 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆89Updated 3 weeks ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆310Updated 3 weeks ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 5 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆91Updated 6 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆101Updated 11 months ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆76Updated last year
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated 2 weeks ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆156Updated 3 weeks ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆127Updated 3 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆102Updated 3 years ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆75Updated last year
• HDLForBeginners / Examples
  ☆90Updated last year
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 3 months ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆91Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆112Updated last year
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆160Updated this week