hamsternz / Rudi-RV32ILinks
A rudimental RISCV CPU supporting RV32I instructions, in VHDL
☆125Updated 5 years ago
Alternatives and similar repositories for Rudi-RV32I
Users that are interested in Rudi-RV32I are comparing it to the libraries listed below
Sorting:
- A set of Wishbone Controlled SPI Flash Controllers☆97Updated 3 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- FuseSoC standard core library☆151Updated 2 months ago
- Verilog implementation of a RISC-V core☆135Updated 7 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- ☆139Updated 3 weeks ago
- Verilog wishbone components☆124Updated 2 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- Mathematical Functions in Verilog☆96Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆60Updated 3 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated 2 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Wishbone interconnect utilities☆44Updated last month
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Verilog digital signal processing components☆170Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆132Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆122Updated 4 years ago
- SpinalHDL Hardware Math Library☆94Updated last year
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆101Updated 7 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆147Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆84Updated 5 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Pipelined RISC-V RV32I Core in Verilog☆41Updated 2 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago