Alternatives and similar repositories for COVID-XS

Users that are interested in COVID-XS are comparing it to the libraries listed below

• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆58Updated 3 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 4 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 6 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• yuehniu / CNN.frequencyFPGA
  CNN Accelerator in Frequency Domain
  ☆12Updated 5 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• valar1234 / SDAI
  An Synthesizable Deep Learning Library based on Xilinx High Level Synthesis(HLS) tool
  ☆15Updated 8 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / logicnets
  ☆94Updated 11 months ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• SCLUO / ITRI-OpenDLA
  OpenDLA for trying the demo and FPGA solution
  ☆16Updated 2 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆47Updated 7 years ago
• PeterOgden / ZCU104_VideoDemo
  PYNQ demo as seen at FPL 2018
  ☆21Updated 4 years ago
• JunnanShan / AlexNet-FPGA-implementation
  This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.
  ☆21Updated 7 years ago
• mohdumar644 / TinyYOLO-BNN
  Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.
  ☆30Updated 6 years ago
• fastmachinelearning / models
  Models and examples built with hls4ml
  ☆12Updated 5 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• williamyang4978 / PipeCNN_Winograd
  An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
  ☆37Updated 4 years ago
• xupgit / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆69Updated 6 years ago
• ralbertazzi / bnn
  Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools
  ☆51Updated 7 years ago
• patryk-oleniuk / cnn_hw_accelerator
  FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ
  ☆21Updated 6 years ago
• kmanev / ZynqUSp-AXI-Speedtest
  ☆14Updated 5 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• ARM-software / DeepFreeze
  ☆40Updated 5 years ago
• sherylll / lenet5-accelerator
  FPGA and GPU acceleration of LeNet5
  ☆35Updated 5 years ago
• tirumalnaidu / opencl-hls-cnn-accelerator
  OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.
  ☆79Updated last year
• walkieq / RNN_HLS
  An LSTM template and a few examples using Vivado HLS
  ☆45Updated last year
• yuehniu / embeddedCNN
  Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.
  ☆25Updated 6 years ago