gewuek / vitis_ai_custom_platform_v1.2_tmpLinks
For v1.2 test
☆12Updated 5 years ago
Alternatives and similar repositories for vitis_ai_custom_platform_v1.2_tmp
Users that are interested in vitis_ai_custom_platform_v1.2_tmp are comparing it to the libraries listed below
Sorting:
- First lesson for you to use DNNDK, also it can be helpful for your AI learning☆77Updated 2 years ago
- This project is trying to create a base vitis platform to run with DPU☆49Updated 5 years ago
- DPU on PYNQ☆242Updated 6 months ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆76Updated 7 years ago
- ☆250Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆51Updated 5 years ago
- ☆497Updated 3 weeks ago
- ☆137Updated 2 months ago
- Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design con…☆114Updated 7 years ago
- Board files to build Ultra 96 PYNQ image☆157Updated 4 months ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆383Updated 2 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆172Updated 6 years ago
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆155Updated 6 years ago
- HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn☆241Updated 4 years ago
- Zynq-7000 DPU TRD☆48Updated 6 years ago
- ☆117Updated 4 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆249Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Updated last year
- FPGA Accelerator for CNN using Vivado HLS☆331Updated 4 years ago
- An LeNet RTL implement onto FPGA☆50Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- ☆48Updated 7 years ago
- Computer Vision Overlays on Pynq☆189Updated 6 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆336Updated 6 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.☆187Updated 9 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Updated last month