olagrottvik / encdec8b10bLinks
Python module for 8B10B encoding and decoding
☆11Updated 2 years ago
Alternatives and similar repositories for encdec8b10b
Users that are interested in encdec8b10b are comparing it to the libraries listed below
Sorting:
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆181Updated 2 weeks ago
- FPGA Logic Analyzer and GUI☆139Updated 2 years ago
- Flexible VHDL library☆189Updated 2 years ago
- SPI Master for FPGA - VHDL and Verilog☆299Updated 2 years ago
- HDL symbol generator☆194Updated 2 years ago
- A huge VHDL library for FPGA and digital ASIC development☆401Updated this week
- Unit testing for cocotb☆162Updated last week
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆74Updated 3 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆67Updated 3 years ago
- Python tools for signal integrity applications☆156Updated last week
- SPI Slave for FPGA in Verilog and VHDL☆212Updated last year
- I2C slave Verilog Design and TestBench☆25Updated 6 years ago
- Library of VHDL components that are useful in larger designs.☆236Updated last year
- ☆104Updated 2 years ago
- Style guide enforcement for VHDL☆222Updated last week
- Simple UART controller for FPGA written in VHDL☆103Updated 4 years ago
- A git-friendly Vivado wrapper☆237Updated last year
- A configurable C++ generator of pipelined Verilog FFT cores☆248Updated last year
- Control and Status Register map generator for HDL projects☆127Updated 4 months ago
- 64-bit RISC-V processor☆16Updated 2 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆164Updated last month
- FPGA and Digital ASIC Build System☆77Updated 3 weeks ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆63Updated 4 years ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆174Updated last year
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆283Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆175Updated 10 months ago
- Course material for a basic hands-on analog circuit design course with IC emphasis☆142Updated last week
- WaveDrom compatible python command line☆108Updated 2 years ago
- VHDL-2008 Support Library☆57Updated 8 years ago
- Vivado and PetaLinux projects for Zynq EBAZ4205 Board☆86Updated 3 years ago