AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.
☆29Apr 6, 2026Updated 5 months ago
Alternatives and similar repositories for eda_ai_assist
Users that are interested in eda_ai_assist are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆26Jul 5, 2026Updated 2 months ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 7 months ago
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects☆55Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Digital Timing Diagram GUI Editor☆38Mar 11, 2026Updated 6 months ago
- The kitchen sink of scripts to aid sw developers☆13Jul 14, 2026Updated 2 months ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 8 months ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- An example model of a Network Processing Unit using the PFPSim framework.☆13Aug 23, 2016Updated 10 years ago
- ☆11Nov 17, 2025Updated 10 months ago
- ☆14Mar 12, 2021Updated 5 years ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆85Aug 10, 2026Updated last month
- “Build It. Test It. Publish It.” This year’s program emphasizes not only open-source design and tapeout, but also reproducible results, m…☆103Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Python module for 8B10B encoding and decoding☆12Jul 25, 2023Updated 3 years ago
- Tutorials on HLS Design☆51Jan 16, 2020Updated 6 years ago
- ☆18Apr 14, 2023Updated 3 years ago
- The lightweight, distributed relational database built on SQLite.☆13Apr 29, 2023Updated 3 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆79Feb 12, 2026Updated 7 months ago
- high level VHDL floating point library for synthesis in fpga☆18Sep 4, 2026Updated 2 weeks ago
- snickerdoodle Linux☆18Sep 10, 2018Updated 8 years ago
- An open source generator for standard cell based memories.☆14Sep 6, 2016Updated 10 years ago
- ☆16Apr 27, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- a mini TPU with floating point arithmetic☆53Dec 22, 2025Updated 9 months ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- Documentation for the 2025 IEEE SSCS Chipathon Track on MOSbius☆19Sep 6, 2025Updated last year
- Probabilistic inference for models of behaviour☆13Mar 5, 2026Updated 6 months ago
- Fast Camera Image Processing Pipeline for Mobile☆23Nov 16, 2025Updated 10 months ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆21Jun 17, 2020Updated 6 years ago
- TRAGEN: A Synthetic Trace Generator for Realistic Cache Simulations☆21Mar 25, 2024Updated 2 years ago
- An intro to embedded systems for ML application developers☆28Jan 30, 2026Updated 7 months ago
- Breakout board for the 74HC4051 8-channel analog multiplexer/demultiplexer☆13May 18, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design u…☆19Sep 3, 2024Updated 2 years ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆28Jan 24, 2026Updated 7 months ago
- QC Study Group Github Repository☆13Dec 15, 2020Updated 5 years ago
- ☆17Aug 25, 2026Updated 3 weeks ago
- ☆20Dec 28, 2021Updated 4 years ago
- ☆12Sep 27, 2020Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆33Feb 11, 2024Updated 2 years ago