oscourse-tsinghua / undergraduate-zwpu2019Links
http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019
☆12Updated 6 years ago
Alternatives and similar repositories for undergraduate-zwpu2019
Users that are interested in undergraduate-zwpu2019 are comparing it to the libraries listed below
Sorting:
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆70Updated 2 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆76Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Updated 6 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆166Updated last year
- 8051 core☆109Updated 11 years ago
- OpenXuantie - OpenE906 Core☆144Updated last year
- USB 2.0 Device IP Core☆71Updated 8 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated 2 years ago
- LicheeTang 蜂鸟E203 Core☆199Updated 6 years ago
- ☆64Updated 10 months ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆22Updated 2 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- Nuclei RISC-V Software Development Kit☆150Updated this week
- OpenXuantie - OpenE902 Core☆161Updated last year
- ☆22Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆145Updated last year
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- ☆37Updated 7 years ago
- Verilog implementation of a RISC-V core☆129Updated 7 years ago
- RISC-V RV32IMAFC Core for MCU☆40Updated 9 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆38Updated 4 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆194Updated 6 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆112Updated 3 years ago
- AHB3-Lite Interconnect☆95Updated last year
- The Ultra-Low Power RISC Core☆15Updated 5 years ago
- Verilog UART☆186Updated 12 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year