Alternatives and similar repositories for undergraduate-zwpu2019

Users that are interested in undergraduate-zwpu2019 are comparing it to the libraries listed below

• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆72Updated 4 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆62Updated 2 years ago
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆23Updated 2 years ago
• freecores / 8051
  8051 core
  ☆107Updated 11 years ago
• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆197Updated 6 years ago
• verimake-team / SparkRoad-V
  ☆64Updated 6 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• riscv-mcu / hbird-sdk
  OpenSource HummingBird RISC-V Software Development Kit
  ☆159Updated last year
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆139Updated last year
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆152Updated last year
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• ilg-archived / riscv-none-gcc
  The GNU MCU Eclipse RISC-V Embedded GCC
  ☆79Updated 5 years ago
• risclite / R8051
  8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.
  ☆185Updated 5 years ago
• redchenjs / wujian100_open
  平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）
  ☆19Updated last year
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆130Updated 5 years ago
• ansonn / esl_systemc
  systemc建模相关
  ☆27Updated 11 years ago
• munetomo-maruyama / mmRISC-1
  RISC-V RV32IMAFC Core for MCU
  ☆38Updated 5 months ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 5 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆121Updated 6 years ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• Nuclei-Software / nuclei-sdk
  Nuclei RISC-V Software Development Kit
  ☆145Updated this week
• rgwan / kamikaze
  Light-weight RISC-V RV32IMC microcontroller core.
  ☆104Updated 8 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆57Updated 9 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆88Updated 4 months ago