Alternatives and similar repositories for udarkrisc:

Users that are interested in udarkrisc are comparing it to the libraries listed below

• olofk / qerv
  ☆15Updated 5 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated 2 years ago
• MichaelBell / nanoV
  RISC-V RV32E core designed for minimal area
  ☆16Updated 5 months ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆21Updated 5 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆55Updated last week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• fm4dd / gatemate-riscv
  RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga
  ☆12Updated 2 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆28Updated 3 weeks ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated last year
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆19Updated 2 weeks ago
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆32Updated 8 years ago
• Mecrisp / Nandland-RISC-V
  RISC-V Playground on Nandland Go
  ☆16Updated 2 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆38Updated last week
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆17Updated 4 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆39Updated 2 years ago
• tomverbeure / sidechan
  Side channel communication test within an FPGA
  ☆11Updated 4 years ago
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆16Updated 2 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆52Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆91Updated 8 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆29Updated 3 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆33Updated 3 weeks ago