Alternatives and similar repositories for udarkrisc

Users that are interested in udarkrisc are comparing it to the libraries listed below

• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• jrmoserbaltimore / risc-v-cpu-asynchronous
  A RISC-V CPU implementation
  ☆14Updated 5 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated this week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 5 months ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆32Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 7 months ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆67Updated this week
• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆41Updated 3 years ago
• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆54Updated 4 years ago
• fredrequin / fpga_1943
  Verilog re-implementation of the famous CAPCOM arcade game
  ☆29Updated 6 years ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆19Updated 4 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆33Updated 8 years ago
• splinedrive / kianFpgaPong
  Basic Pong you can extend with rotary, sound, vga generator and autopilot
  ☆11Updated 3 years ago
• Mr-Bossman / KISC-V
  KISCV, a KISS principle riscv32i CPU
  ☆25Updated 8 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆61Updated last year
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆32Updated last year
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆17Updated 3 years ago
• gatecat / hrt
  Hot Reconfiguration Technology demo
  ☆40Updated 3 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆106Updated last month
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆97Updated 3 years ago
• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆22Updated 10 months ago
• ToNi3141 / RasterIX
  OpenGL 1.x implementation for FPGAs
  ☆100Updated last week
• fontamsoc / pu32
  ☆15Updated 4 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated last week
• jevinskie / riscv-smol-linux-kernel
  Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM
  ☆24Updated 2 years ago
• Mecrisp / Nandland-RISC-V
  RISC-V Playground on Nandland Go
  ☆16Updated 2 years ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆56Updated 5 months ago